Abstract: Hierarchical and lightweight imitation learning (IL) for power management of embedded systems-on-chip (SoCs), also referred to herein as HiLITE, is provided. Modern SoCs use dynamic power management (DPM) techniques to improve energy efficiency. However, existing techniques are unable to efficiently adapt the runtime decisions considering multiple objectives (e.g., energy and real-time requirements) simultaneously on heterogeneous platforms. To address this need, embodiments described herein propose HiLITE, a hierarchical IL framework that maximizes energy efficiency while satisfying soft real-time constraints on embedded SoCs. This approach first trains DPM policies using IL; then, it applies a regression policy at runtime to minimize deadline misses. HiLITE improves the energy-delay product by 40% on average, and reduces deadline misses by up to 76%, compared to state-of-the-art approaches.

Abstract: Hierarchical and lightweight imitation learning (IL) for power management of embedded systems-on-chip (SoCs), also referred to herein as HiLITE, is provided. Modern SoCs use dynamic power management (DPM) techniques to improve energy efficiency. However, existing techniques are unable to efficiently adapt the runtime decisions considering multiple objectives (e.g., energy and real-time requirements) simultaneously on heterogeneous platforms. To address this need, embodiments described herein propose HiLITE, a hierarchical IL framework that maximizes energy efficiency while satisfying soft real-time constraints on embedded SoCs. This approach first trains DPM policies using IL; then, it applies a regression policy at runtime to minimize deadline misses. HiLITE improves the energy-delay product by 40% on average, and reduces deadline misses by up to 76%, compared to state-of-the-art approaches.

Abstract: Provided herein are dynamic adaptive scheduling (DAS) systems. In some embodiments, the DAS systems include a first scheduler, a second scheduler that is slower than the first scheduler, and a runtime preselection classifier that is operably connected to the first scheduler and the second scheduler, which runtime preselection classifier is configured to effect selective use of the first scheduler or the second scheduler to perform a given scheduling task. Related systems, computer readable media, and additional methods are also provided.

Abstract: A user-space emulation framework for heterogeneous system-on-chip (SoC) design is provided. Embodiments described herein propose a portable, Linux-based emulation framework to provide an ecosystem for hardware-software co-design of heterogenous SoCs (e.g., domain-specific SoCs (DSSoCs)) and enable their rapid evaluation during the pre-silicon design phase. This framework holistically targets three key challenges of heterogeneous SoC design: accelerator integration, resource management, and application development. These challenges are addressed via a flexible and lightweight user-space runtime environment that enables easy integration of new accelerators, scheduling heuristics, and user applications, and the utility of each is illustrated through various case studies. A prototype compilation toolchain is introduced that enables automatic mapping of unlabeled C code to heterogeneous SoC platforms.

Abstract: Runtime task scheduling using imitation learning (IL) for heterogenous many-core systems is provided. Domain-specific systems-on-chip (DSSoCs) are recognized as a key approach to narrow down the performance and energy-efficiency gap between custom hardware accelerators and programmable processors. Reaching the full potential of these architectures depends critically on optimally scheduling the applications to available resources at runtime. Existing optimization-based techniques cannot achieve this objective at runtime due to the combinatorial nature of the task scheduling problem. In an exemplary aspect described herein, scheduling is posed as a classification problem, and embodiments propose a hierarchical IL-based scheduler that learns from an Oracle to maximize the performance of multiple domain-specific applications. Extensive evaluations show that the proposed IL-based scheduler approximates an offline Oracle policy with more than 99% accuracy for performance- and energy-based optimization objectives.

Abstract: Hierarchical and lightweight imitation learning (IL) for power management of embedded systems-on-chip (SoCs), also referred to herein as HiLITE, is provided. Modern SoCs use dynamic power management (DPM) techniques to improve energy efficiency. However, existing techniques are unable to efficiently adapt the mntime decisions considering multiple objectives (e.g., energy and real-time requirements) simultaneously on heterogeneous platforms. To address this need, embodiments described herein propose HiLITE, a hierarchical IL framework that maximizes energy efficiency while satisfying soft real-time constraints on embedded SoCs. This approach first trains DPM policies using IL; then, it applies a regression policy at runtime to minimize deadline misses. HiLITE improves the energy-delay product by 40% on average, and reduces deadline misses by up to 76%, compared to state-of-the-art approaches.

Abstract: A method of producing a reconfigurable circuit device for running a computer program of moderate complexity such as multimedia processing. Code for the application is compiled into Control Flow Graphs representing distinct parts of the application to be run. From those Control Flow Graphs are extracted basic blocks. The basic blocks are converted to Data Flow Graphs by a compiler utility. From two or more Data Flow Graphs, a largest common subgraph is determined. The largest common subgraph is ASAP scheduled and substituted back into the Data Flow Graphs which also have been scheduled. The separate Data Flow Graphs containing the scheduled largest common subgraph are converted to data paths that are then combined to form code for operating the application. The largest common subgraph is effected in hardware that is shared among the parts of the application from which the Data Flow Graphs were developed.

Abstract: A method of producing a reconfigurable circuit device for running a computer program of moderate complexity such as multimedia processing. Code for the application is compiled into Control Flow Graphs representing distinct parts of the application to be run. From those Control Flow Graphs are extracted basic blocks. The basic blocks are converted to Data Flow Graphs by a compiler utility. From two or more Data Flow Graphs, a largest common subgraph is determined. The largest common subgraph is ASAP scheduled and substituted back into the Data Flow Graphs which also have been scheduled. The separate Data Flow Graphs containing the scheduled largest common subgraph are converted to data paths that are then combined to form code for operating the application. The largest common subgraph is effected in hardware that is shared among the parts of the application from which the Data Flow Graphs were developed.