Abstract: An electronic circuit for measuring an angle and an intensity of an external magnetic field, includes: first and second magnetic field sensing units having sensing axes substantially orthogonal to each other; a voltage generator supplying a synchronization signal, a first voltage waveform to the first magnetic field sensing unit and a second voltage waveform to the second magnetic field sensing unit; a signal conditioning unit configured for adding the first and second sensing output signals and outputting a conditioned signal. The first and second voltage waveforms have substantially the same amplitude and frequency and are phase shifted by about 90° with respect to each other. The conditioned signal and the synchronization signal are inputted into a magnetic field angle detection unit configured for measuring a phase shift between the conditioned signal and the synchronization signal and for determining the angle of the external magnetic field from the measured phase shift.

Abstract: A reader device for reading information stored on a magnetic strip containing a plurality of polarized magnets, each providing a magnetic flux, said reader device including: a magnetoresistive sensor including a plurality of magnetoresistive elements and configured for reading the information stored on the magnetic strip and outputting a read signal; a processing module configured for decoding the read signal and extracting binary data; wherein the read signal includes amplitude information of the magnetic flux; and wherein the processing module is further configured for decoding the read signal using the amplitude information of the read signal is described. Further, an amplitude decoding method for decoding the read signal outputted by the reader device is described.

Abstract: The present disclosure concerns a magnetic reader (MR) sensor device for reading magnetic stripes, the MR sensor device comprising a substrate provided on a wafer, a back-end-of-line (BEOL) interconnect layer and a plurality of magneto-resistive sensor elements embedded within the BEOL interconnect layer; the MR sensor device comprising a protective layer having a Vickers hardness of at least 3 GPa. The present disclosure further concerns a method for manufacturing the MR sensor device. The MR sensor device can be brought close to the surface to the magnetic stripe so that the magnetic stripe can be read with an increased resolution.

Abstract: An electronic circuit for measuring an angle and an intensity of an external magnetic field, includes: first and second magnetic field sensing units having sensing axes substantially orthogonal to each other; a voltage generator supplying a synchronization signal, a first voltage waveform to the first magnetic field sensing unit and a second voltage waveform to the second magnetic field sensing unit; a signal conditioning unit configured for adding the first and second sensing output signals and outputting a conditioned signal. The first and second voltage waveforms have substantially the same amplitude and frequency and are phase shifted by about 90° with respect to each other. The conditioned signal and the synchronization signal are inputted into a magnetic field angle detection unit configured for measuring a phase shift between the conditioned signal and the synchronization signal and for determining the angle of the external magnetic field from the measured phase shift.

Abstract: A reader device for reading information stored on a magnetic strip containing a plurality of polarized magnets, each providing a magnetic flux, said reader device including: a magnetoresistive sensor including a plurality of magnetoresistive elements and configured for reading the information stored on the magnetic strip and outputting a read signal; a processing module configured for decoding the read signal and extracting binary data; wherein the read signal includes amplitude information of the magnetic flux; and wherein the processing module is further configured for decoding the read signal using the amplitude information of the read signal is described. Further, an amplitude decoding method for decoding the read signal outputted by the reader device is described.

Abstract: The present disclosure concerns a magnetic reader (MR)sensor device for reading magnetic stripes, the MR sensor device comprising a substrate provided on a wafer, a back-end-of-line (BEOL) interconnect layer and a plurality of magneto-resistive sensor elements embedded within the BEOL interconnect layer; the MR sensor device comprising a protective layer having a Vickers hardness of at least 3 GPa. The present disclosure further concerns a method for manufacturing the MR sensor device. The MR sensor device can be brought close to the surface to the magnetic stripe so that the magnetic stripe can be read with an increased resolution.

Abstract: An MLU-based accelerometer including: at least one MLU including a tunnel barrier layer between a first magnetic layer having a fixed first magnetization direction and a second magnetic layer having a second magnetization direction that can be varied. A proof-mass includes a ferromagnetic material having a proof-mass magnetization inducing a proof-mass field, the proof-mass being elastically suspended such as to be deflected in at least one direction when subjected to an acceleration vector. The proof-mass is magnetically coupled to the MLU cell via the proof-mass field. A read module is configured for determining a magnetoresistance of each MLU cell such as to determine an acceleration vector from the deflection of the proof-mass relative to any one of the at least one MLU cell.

Abstract: A logic gate module for performing logic functions including a MRAM cell including a magnetic tunnel junction comprising a sense layer, a storage layer, and a spacer layer. The MRAM cell has a junction resistance determined by the degree of alignment between a sense magnetization of the sense layer and the storage magnetization of the storage layer. The storage magnetization and the sense magnetization are switchable between m directions to store data corresponding to one of m logic states, with m>2, such that the MRAM cell is usable as a n-bit cell with n?2. The logic gate module further includes a comparator for comparing the junction resistance with a reference value and outputting a digital signal indicating a difference between the junction resistance and the reference value, such that logic functions can be performed.

Abstract: A logic gate module for performing logic functions including a MRAM cell including a magnetic tunnel junction comprising a sense layer, a storage layer, and a spacer layer. The MRAM cell has a junction resistance determined by the degree of alignment between a sense magnetization of the sense layer and the storage magnetization of the storage layer. The storage magnetization and the sense magnetization are switchable between m directions to store data corresponding to one of m logic states, with m>2, such that the MRAM cell is usable as a n-bit cell with n?2. The logic gate module further includes a comparator for comparing the junction resistance with a reference value and outputting a digital signal indicating a difference between the junction resistance and the reference value, such that logic functions can be performed.

Abstract: A memory protection device for controlling access to a memory and a method of controlling access to a memory are disclosed. A memory status value held by latch circuitry in the memory protection device determines whether the memory is an enabled or a disabled state. After power-up, a power-on-reset signal causes the memory status value to indicate the enabled state. In response to the assertion from a received control signal a memory kill signal is generated by the memory protection device which causes the memory status value to switch to its disabled state and the memory status value then cannot be changed back to the enabled state without a power reset. The memory status value being in the disabled state causes enable signal generation circuitry of the memory to openly be able to generate its read enable signal and write enable signal in a disabled state, thus preventing access to the memory.

Abstract: An MLU-based accelerometer including: at least one MLU including a tunnel barrier layer between a first magnetic layer having a fixed first magnetization direction and a second magnetic layer having a second magnetization direction that can be varied. A proof-mass includes a ferromagnetic material having a proof-mass magnetization inducing a proof-mass field, the proof-mass being elastically suspended such as to be deflected in at least one direction when subjected to an acceleration vector. The proof-mass is magnetically coupled to the MLU cell via the proof-mass field. A read module is configured for determining a magnetoresistance of each MLU cell such as to determine an acceleration vector from the deflection of the proof-mass relative to any one of the at least one MLU cell.

Abstract: A memory protection device for controlling access to a memory and a method of controlling access to a memory are disclosed. A memory status value held by latch circuitry in the memory protection device determines whether the memory is an enabled or a disabled state. After power-up, a power-on-reset signal causes the memory status value to indicate the enabled state. In response to the assertion from a received control signal a memory kill signal is generated by the memory protection device which causes the memory status value to switch to its disabled state and the memory status value then cannot be changed back to the enabled state without a power reset. The memory status value being in the disabled state causes enable signal generation circuitry of the memory to openly be able to generate its read enable signal and write enable signal in a disabled state, thus preventing access to the memory.

Abstract: The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array. Further, erase signal generation circuitry is configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses. The erase signal generation circuitry is further configured to issue said erase signal in said asserted state if the control signal does not take the form of said pulse signal.

Abstract: The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array. Further, erase signal generation circuitry is configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses. The erase signal generation circuitry is further configured to issue said erase signal in said asserted state if the control signal does not take the form of said pulse signal.