Abstract: A power amplifier circuit including a plurality of analog power amplifiers configured to generate a output power for an output signal; at least one processor configured to: select a highest output power signal; determine an input signal power of a modulated signal; determine an output signal power based on the input signal power; compare the output signal power and the highest output power; and disable a subset of the plurality of analog power amplifiers based on the comparison, wherein a remainder of the plurality of analog power amplifiers are configured to generate the output signal power.

Abstract: A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.

Abstract: A power amplifier may be configured to operate in an on state and an off state. The power amplifier may include a plurality of transistors and an impedance controller circuit. The plurality of transistors may be electrically coupled to an electrical ground and an output of the power amplifier. The impedance controller circuit may be electrically coupled to the plurality of transistors and a reference voltage. The impedance controller circuit may be configured to provide the reference voltage to the plurality of transistors when the power amplifier is in the off state to cause a leakage current to flow between the reference voltage and the electrical ground.

Abstract: For example, an apparatus may include a digitally-controlled frequency multiplier, which may be controllable according to a digital control input, to generate an output frequency signal having an output frequency, for example, by multiplying an input frequency of an input frequency signal. For example, the digitally-controlled frequency multiplier may include a phase generator configured to generate a plurality of phase-shifted signal groups corresponding to a respective plurality of first phase-shifts applied to the input frequency signal, a plurality of digital clock multipliers controllable according to the digital control input to generate a respective plurality of frequency-multiplied signals based on the plurality of phase-shifted signal groups, and a combiner to generate the output frequency signal based on a combination of the plurality of frequency-multiplied signals.

Abstract: A switched capacitor digital power amplifier (DPA) or a digital-to-analog converter (DAC) is disclosed. The DPA/DAC includes a plurality of switched capacitor cells connected in parallel. Each switched capacitor cell includes a capacitor and a switch. The switch selectively drives the capacitor in response to an input digital codeword. The switched capacitor cells are divided into sub-arrays and a series capacitor is inserted in series between two adjacent sub-arrays of switched capacitor cells. All the sub-arrays of switched capacitor cells may be in a unary-coded structure. Alternatively, at least one of the sub-arrays may be in a C-2C structure and at least one another sub-array may be in a unary-coded structure. The switch in the switched capacitor cells is driven by a local oscillator signal, and a phase correction buffer may be added for adjusting a delay of the local oscillator signal supplied to sub-arrays of switched capacitor cells.

Abstract: Embodiments of the disclosure are drawn to apparatuses a hybrid switched capacitor array power amplifier (H-SCPA). The H-SCPA may have an array of storage elements divided into sub-arrays. A first sub-array may be configured to receive a delta sigma modulated (DSM) signal. A second sub-array may be configured to receive a Nyquist-rate signal. The H-SCPA may provide an output based on the received DSM and Nyquist-rate signals. The first sub-array and second sub-array may have different architectures. The DSM signal may represent the least significant bits of the signal and the Nyquist-rate signal may represent the most significant bits of the signal.

Abstract: Embodiments of the disclosure are drawn to a low-voltage temperature sensor. The temperature sensor may include a waveform generator, a complementary-to-absolute-temperature (CTAT) voltage generator, a voltage reference, two comparators, and digital logic. A waveform of the waveform generator may be compared to both the CTAT voltage and the voltage reference. The output of the comparison of the CTAT and the waveform may be a pulse-width modulated signal that is temperature-dependent. The output of the comparison of the voltage reference and the waveform may be a signal with constant pulse width. The digital logic may receive the pulsed signals and take a ratio of the two signals to determine a temperature.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for a tunable digital power amplifier (DPA). The tunable DPA may be coupled to a reconfigurable capacitor to form a frequency tunable DPA. The capacitance of the reconfigurable capacitor may be adjusted to optimize the DPA to operate at a desired frequency band. The single tunable DPA may operate over a wide range of frequencies.

Abstract: A switched capacitor digital power amplifier (DPA) or a digital-to-analog converter (DAC) is disclosed. The DPA/DAC includes a plurality of switched capacitor cells connected in parallel. Each switched capacitor cell includes a capacitor and a switch. The switch selectively drives the capacitor in response to an input digital codeword. The switched capacitor cells are divided into sub-arrays and a series capacitor is inserted in series between two adjacent sub-arrays of switched capacitor cells. All the sub-arrays of switched capacitor cells may be in a unary-coded structure. Alternatively, at least one of the sub-arrays may be in a C-2C structure and at least one another sub-array may be in a unary-coded structure. The switch in the switched capacitor cells is driven by a local oscillator signal, and a phase correction buffer may be added for adjusting a delay of the local oscillator signal supplied to sub-arrays of switched capacitor cells.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for transmission beamforming. A multiphase beam steering transmitter may include a transmitter array of multiple transmitters. A transmitter may include a multiphase logic decoder that directly controls a power amplifier to perform a vector addition of a beam phase and amplitude. A transmitter of the array may include a multiphase clock generator that outputs basis phases with embedded phase modulation data which are output to the multiphase logic decoder. The multiphase clock generator may receive a modulated clock signal. The PA may be a multiphase switched capacitor power amplifier. The multiphase logic decoder may output two phases adjacent to a desired phase as inputs to clocks of the SCPA. The multiphase logic decoder may further output a control signal that determines which cells in the SCPA are activated and when.

Abstract: Embodiments of the disclosure are drawn to voltage reference circuits and methods of designing same. The voltage reference circuit may include a main stage and one or more auxiliary stages. The output of the main stage may be a reference voltage. The auxiliary stages may provide a feedback voltage that reduces a temperature dependence of the reference voltage. Each stage may include two or more transistors. The transistors may operate in a sub-threshold mode to provide the reference voltage.

Abstract: Embodiments of the disclosure are drawn to a low-voltage temperature sensor. The temperature sensor may include a waveform generator, a complementary-to-absolute-temperature (CTAT) voltage generator, a voltage reference, two comparators, and digital logic. A waveform of the waveform generator may be compared to both the CTAT voltage and the voltage reference. The output of the comparison of the CTAT and the waveform may be a pulse-width modulated signal that is temperature-dependent. The output of the comparison of the voltage reference and the waveform may be a signal with constant pulse width. The digital logic may receive the pulsed signals and take a ratio of the two signals to determine a temperature.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for a tunable digital power amplifier (DPA). The tunable DPA may be coupled to a reconfigurable capacitor to form a frequency tunable DPA. The capacitance of the reconfigurable capacitor may be adjusted to optimize the DPA to operate at a desired frequency band. The single tunable DPA may operate over a wide range of frequencies.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for transmission beamforming. A multiphase beam steering transmitter may include a transmitter array of multiple transmitters. A transmitter may include a multiphase logic decoder that directly controls a power amplifier to perform a vector addition of a beam phase and amplitude. A transmitter of the array may include a multiphase clock generator that outputs basis phases with embedded phase modulation data which are output to the multiphase logic decoder. The multiphase clock generator may receive a modulated clock signal. The PA may be a multiphase switched capacitor power amplifier. The multiphase logic decoder may output two phases adjacent to a desired phase as inputs to clocks of the SCPA. The multiphase logic decoder may further output a control signal that determines which cells in the SCPA are activated and when.

Abstract: Embodiments of the disclosure are drawn to apparatuses a hybrid switched capacitor array power amplifier (H-SCPA). The H-SCPA may have an array of storage elements divided into sub-arrays. A first sub-array may be configured to receive a delta sigma modulated (DSM) signal. A second sub-array may be configured to receive a Nyquist-rate signal. The H-SCPA may provide an output based on the received DSM and Nyquist-rate signals. The first sub-array and second sub-array may have different architectures. The DSM signal may represent the least significant bits of the signal and the Nyquist-rate signal may represent the most significant bits of the signal.