Abstract: A digital unit-cell included in an imaging system includes a light sensor configured to generate an electrical charge in response to receiving light, and an energy storage circuit configured to establish a first parasitic capacitance and second large capacitance to store the electrical charge. The digital unit-cell further includes a gain selection circuit and a dual-mode comparator. The gain selection circuit is configured operate in a first mode to invoke the first capacitance and a second mode to invoke the second capacitance. The dual-mode comparator is configured to operate in a first reset mode that generates a first reset signal having a first pulse duration and a second reset mode that generates a second reset signal having a second pulse duration that is a longer than the first pulse duration.

Abstract: A digital unit-cell included in an imaging system includes a light sensor configured to generate an electrical charge in response to receiving light, and an energy storage circuit configured to establish a first parasitic capacitance and second large capacitance to store the electrical charge. The digital unit-cell further includes a gain selection circuit and a dual-mode comparator. The gain selection circuit is configured operate in a first mode to invoke the first capacitance and a second mode to invoke the second capacitance. The dual-mode comparator is configured to operate in a first reset mode that generates a first reset signal having a first pulse duration and a second reset mode that generates a second reset signal having a second pulse duration that is a longer than the first pulse duration.

Abstract: A class AB amplifier includes an input stage having a pair of differential input terminals, first and second differential output terminals, and a local common mode feedback circuit. The input stage includes a local common mode feedback circuit having cascode transistor to achieve relatively high gain. The amplifier also includes an output stage having first and second pairs complementary transistors coupled between first and second power supply nodes. One of the complementary transistors in each pair has a gate coupled to the first and second differential output terminals, respectively. The output stage includes a pair of cascode transistor connected to one of the pairs of complementary output transistors. The amplifier can be used to supply a bias voltage to a highly capacitive load, such as voltage sampling capacitors in a CMOS imager.

Abstract: The various embodiments disclose capacitor multiplier circuits that may be integrated into imaging devices, such as for semiconductor Complimentary Metal Oxide Semiconductor (CMOS) image sensors, to create an effective capacitance in response to a low frequency, such as row-wise temporal noise, that may be generated along a row of image sensor pixels. The created effective capacitance from any one of the capacitor multiplier circuits along with a small signal resistance created by a trans-conductance of a current biasing transistor form a low pass filter that will attenuate the low frequency noise.

Abstract: A master bias current generating circuit includes a current source, a first reference leg, and a second reference leg. The first reference leg includes a first transistor having a first size parameter coupled to the current source and a first diode having a second size parameter coupled to the first transistor. The second reference leg includes a second transistor having a third size parameter less than the first size parameter coupled to the current source and a second diode having a fourth size parameter greater than the second size parameter coupled to the second transistor.

Abstract: A class AB amplifier includes an input stage having a pair of differential input terminals, first and second differential output terminals, and a local common mode feedback circuit. The input stage includes a local common mode feedback circuit having cascode transistor to achieve relatively high gain. The amplifier also includes an output stage having first and second pairs complementary transistors coupled between first and second power supply nodes. One of the complementary transistors in each pair has a gate coupled to the first and second differential output terminals, respectively. The output stage includes a pair of cascode transistor connected to one of the pairs of complementary output transistors. The amplifier can be used to supply a bias voltage to a highly capacitive load, such as voltage sampling capacitors in a CMOS imager.

Abstract: The various embodiments disclose capacitor multiplier circuits that may be integrated into imaging devices, such as for semiconductor Complimentary Metal Oxide Semiconductor (CMOS) image sensors, to create an effective capacitance in response to a low frequency, such as row-wise temporal noise, that may be generated along a row of image sensor pixels. The created effective capacitance from any one of the capacitor multiplier circuits along with a small signal resistance created by a trans-conductance of a current biasing transistor form a low pass filter that will attenuate the low frequency noise.

Abstract: A master bias current generating circuit includes a current source, a first reference leg, and a second reference leg. The first reference leg includes a first transistor having a first size parameter coupled to the current source and a first diode having a second size parameter coupled to the first transistor. The second reference leg includes a second transistor having a third size parameter less than the first size parameter coupled to the current source and a second diode having a fourth size parameter greater than the second size parameter coupled to the second transistor.

Abstract: A pipelined analog-to-digital converter features an amplifier block that includes a switching network to implement a double sampling and double conversion principle of operation. The amplifier block utilizes both phases of a clock for sampling and conversion. Additionally, each stage of the analog-to-digital converter is associated with two independent processing blocks. The analog-to-digital converter can achieve double throughput for approximately the same level of power consumption. Alternatively, throughput may be maintained, but the gain-bandwidth of the amplifier block may be reduced by half, thereby halving the DC bias current consumed by the amplifier. Additionally, the output signal of the amplifier itself is not reset to a common mode voltage.

Abstract: An implantable stimulation device has a sensing amplifier circuit for amplifying low amplitude cardiac signals, while maintaining low power, to produce an output signal having a low noise level. The sense amplifier circuit includes a two-stage amplifier, a bandpass filter, and a threshold detector. The first stage comprises a linear differential amplifier which has low gain, good common mode rejection, and a current consumption proportional to the gain. The second stage is a switched-capacitor amplifier which has a programmable gain and low current consumption. The noise content of the system is low and produced substantially entirely in the switched-capacitor amplifier.

Abstract: A low-power band-pass filter for use in a cardiac pacer includes a single operational amplifier connected in circuit relationship with a plurality of switched capacitors that function as bilinear resistors. Each bilinear resistor comprises a switch for coupling a first lead of a capacitive element to a first terminal and for coupling a second lead of the capacitive element to a second terminal in response to a first state of a control signal, and for coupling the first lead of the capacitive element to the second terminal and for coupling the second lead of the capacitive element to the first terminal in response to a second state of the control signal. Thus, the bilinear resistor switches or oscillates the electrical orientation of the capacitive element between the first terminal and the second terminal in response to the first and second states of the control signal. The invention also includes a method of operating such an implantable filter circuit.

Abstract: A sense amplifier adapted for use with a cardiac pacer or the like includes a constant gain filter, a window comparator circuit and a programmable threshold reference generator circuit. The reference generator circuit generates a programmable window (reference) voltage used by the window comparator circuit to determine whether an input signal, amplified by the constant gain filter, exceeds the window voltage. The reference generator circuit is based on a bipolar junction device having an adjustable emitter area through which a constant current flows. The emitter area is adjusted in response to a control signal. As the emitter area changes as controlled by the control signal, the voltage across the device changes. In a preferred embodiment, a parallel combination or network of switched bipolar junction devices is used to realize the adjustable emitter area.