Abstract: The disclosed chip is suitable for VLSI dRAMS. The memory cell includes a bipolar transistor, a JFET, and a capacitor. The capacitor comprises a MOSFET which is operated only in the accumulation mode. Each cell requires only three lines. On a p-substrate, which comprises the collector of the bipolar, the cell layers are:- an n-well which comprises the channel of the JFET and the base of the bipolar; a p-region, which comprises the gate of the JFET, the emitter of the bipolar, and the bottom plate of the capacitor; an oxide layer; and a conducting layer; arranged as a vertical stack in that order. The latter two layers are the insulator and the top plate of the capacitor. The source and drain of the JFET are respective n+ regions placed one either side of the stack. The n-well can be deep and hence can be compatible with conventional CMOS technology. The chip has full read, write, and refresh capability; is relatively easily manufactured; and can be considerably scaled down without losing performance.