Patents by Inventor Ali I. Sheikh

Ali I. Sheikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10133652
    Abstract: Embodiments of the present invention provide a method, computer program product, and system for debugging optimized code. The system includes a FAT binary, wherein the FAT binary comprises a non-optimized native code and an internal representation of a program's source code. An optimus program is configured to transform the internal representation of the program's source code into a fully optimized native code. The system also includes an enhanced loader, wherein the enhanced loader is configured to communicate with a debugger to determine a type of code to load.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Moniz, Ali I. Sheikh, Diana P. Sutandie, Srivatsan Vijayakumar, Ying Di Zhang
  • Patent number: 9940218
    Abstract: Embodiments of the present invention provide a method, computer program product, and system for debugging optimized code. The system includes a FAT binary, wherein the FAT binary comprises a non-optimized native code and an internal representation of a program's source code. An optimus program is configured to transform the internal representation of the program's source code into a fully optimized native code. The system also includes an enhanced loader, wherein the enhanced loader is configured to communicate with a debugger to determine a type of code to load.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Moniz, Ali I. Sheikh, Diana P. Sutandie, Srivatsan Vijayakumar, Ying Di Zhang
  • Patent number: 9858054
    Abstract: A method for optimizing binary code in a language having access to binary coded decimal variable. The method includes: generating a first compiler expression of the binary code; analyzing a use-definition and/or a definition-use for the first compiler expression; generating a second compiler expression by identifying logical binary coded decimal (BCD) variables in the first compiler expression; assigning temporary variables to the logical BCD variables, wherein the second compiler expression includes packed decimal operations and the assigned temporary variables; and converting a packed decimal operation in the second compiler expression and an assigned temporary variable to a decimal floating point (DFP) if sign information and precision information are not lost during conversion from BCD to DFP, wherein identifying logical BCD variables includes: in the use-definition and/or definition-use of operands, regarding an operand of definition and an operand of use as the same logical BCD variables.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshihiko Koju, Ali I Sheikh
  • Publication number: 20170371767
    Abstract: Embodiments of the present invention provide a method, computer program product, and system for debugging optimized code. The system includes a FAT binary, wherein the FAT binary comprises a non-optimized native code and an internal representation of a program's source code. An optimus program is configured to transform the internal representation of the program's source code into a fully optimized native code. The system also includes an enhanced loader, wherein the enhanced loader is configured to communicate with a debugger to determine a type of code to load.
    Type: Application
    Filed: September 15, 2017
    Publication date: December 28, 2017
    Inventors: Michael J. Moniz, Ali I. Sheikh, Diana P. Sutandie, Srivatsan Vijayakumar, Ying Di Zhang
  • Publication number: 20170235666
    Abstract: Embodiments of the present invention provide a method, computer program product, and system for debugging optimized code. The system includes a FAT binary, wherein the FAT binary comprises a non-optimized native code and an internal representation of a program's source code. An optimus program is configured to transform the internal representation of the program's source code into a fully optimized native code. The system also includes an enhanced loader, wherein the enhanced loader is configured to communicate with a debugger to determine a type of code to load.
    Type: Application
    Filed: February 15, 2016
    Publication date: August 17, 2017
    Inventors: Michael J. Moniz, Ali I. Sheikh, Diana P. Sutandie, Srivatsan Vijayakumar, Ying Di Zhang
  • Publication number: 20160154635
    Abstract: A method for optimizing binary code in a language having access to binary coded decimal variable. The method includes: generating a first compiler expression of the binary code; analyzing a use-definition and/or a definition-use for the first compiler expression; generating a second compiler expression by identifying logical binary coded decimal (BCD) variables in the first compiler expression; assigning temporary variables to the logical BCD variables, wherein the second compiler expression includes packed decimal operations and the assigned temporary variables; and converting a packed decimal operation in the second compiler expression and an assigned temporary variable to a decimal floating point (DFP) if sign information and precision information are not lost during conversion from BCD to DFP, wherein identifying logical BCD variables includes: in the use-definition and/or definition-use of operands, regarding an operand of definition and an operand of use as the same logical BCD variables.
    Type: Application
    Filed: February 5, 2016
    Publication date: June 2, 2016
    Inventors: TOSHIHIKO KOJU, ALI I SHEIKH
  • Patent number: 9280328
    Abstract: A method for optimizing binary code in a language having access to binary coded decimal variable. The method includes: generating a first compiler expression of the binary code; analyzing a use-definition and/or a definition-use for the first compiler expression; generating a second compiler expression by identifying logical binary coded decimal (BCD) variables in the first compiler expression; assigning temporary variables to the logical BCD variables, wherein the second compiler expression includes packed decimal operations and the assigned temporary variables; and converting a packed decimal operation in the second compiler expression and an assigned temporary variable to a decimal floating point (DFP) if sign information and precision information are not lost during conversion from BCD to DFP, wherein identifying logical BCD variables includes: in the use-definition and/or definition-use of operands, regarding an operand of definition and an operand of use as the same logical BCD variables.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: March 8, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshihiko Koju, Ali I Sheikh
  • Patent number: 9158566
    Abstract: Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Theodore J Bohizic, Reid T Copeland, Marcel Mitran, Ali I Sheikh
  • Patent number: 8949106
    Abstract: A selected group of Guest machine instructions in an emulation environment are translated to a semantic routine of Host machine instructions, wherein Guest cells corresponding to an opcode portion of a Guest instruction are mapped to corresponding Host cells, wherein the semantic routine of Host machine instructions are patched into a Host cell corresponding to the first Guest cell of the group of Guest machine instructions, wherein other Host cells of the corresponding Host cells are patched with semantic routines for emulating single instructions associated with the corresponding Guest cell.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
  • Publication number: 20140317608
    Abstract: A method for optimizing binary code in a language having access to binary coded decimal variable. The method includes: generating a first compiler expression of the binary code; analyzing a use-definition and/or a definition-use for the first compiler expression; generating a second compiler expression by identifying logical binary coded decimal (BCD) variables in the first compiler expression; assigning temporary variables to the logical BCD variables, wherein the second compiler expression includes packed decimal operations and the assigned temporary variables; and converting a packed decimal operation in the second compiler expression and an assigned temporary variable to a decimal floating point (DFP) if sign information and precision information are not lost during conversion from BCD to DFP, wherein identifying logical BCD variables includes: in the use-definition and/or definition-use of operands, regarding an operand of definition and an operand of use as the same logical BCD variables.
    Type: Application
    Filed: April 9, 2014
    Publication date: October 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshihiko Koju, Ali I. Sheikh
  • Patent number: 8869128
    Abstract: A method, program, and apparatus for optimizing compiled code using a dynamic compiler. The method includes the steps of: generating intermediate code from a trace, which is an instruction sequence described in machine language; computing an offset between an address value, which is a base point of an indirect branch instruction, and a start address of a memory page, which includes a virtual address referred to by the information processing apparatus immediately after processing a first instruction; determining whether an indirect branch instruction that is subsequent to the first instruction causes processing to jump to another memory page, by using a value obtained from adding the offset to a displacement made by the indirect branch instruction; and optimizing the intermediate code by using the result of the determining step.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Toshihiko Koju, Ali I Sheikh, Xin Tong
  • Patent number: 8819647
    Abstract: Nested virtual machines cooperate with one another to improve system performance. In particular, an outer virtual machine performs tasks on behalf of an inner virtual machine to improve system performance. One such task includes translation of instructions for the inner virtual machine.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Marcel Mitran, Ali I. Sheikh
  • Patent number: 8768683
    Abstract: A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Theodore J Bohizic, Reid T Copeland, Marcel Mitran, Ali I Sheikh
  • Publication number: 20140136179
    Abstract: Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Theodore J Bohizic, Reid T Copeland, Marcel Mitran, Ali I Sheikh
  • Patent number: 8713289
    Abstract: Emulation of source machine instructions is provided in which target machine CPU condition codes are employed to produce emulated condition code settings without the use, encoding or generation of branching instructions.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Reid T. Copeland, Patrick R. Doyle, Charles B. Hall, Andrew Johnson, Ali I. Sheikh
  • Patent number: 8689198
    Abstract: A compiling system and method for optimizing binary code. The method includes the step of replacing a memory access on a stack area in order to save a value of a register with local variable access. The method further includes: giving a call number to a call instruction and an inlined code in response to an inline expansion of a code to be called by the call instruction; creating a parent-child relationship information for at least one of the call number; processing the memory accesses with an escaped stack pointer as a base address if a stack pointer has escaped; prohibiting a replacement of a prohibited memory access if the stack pointer has escaped; and replacing unprohibited memory access with the local variable access if the stack pointer has escaped.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Motohiro Kawahito, Ali I. Sheikh, Vijay Sundaresan
  • Publication number: 20130231913
    Abstract: A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction.
    Type: Application
    Filed: April 19, 2013
    Publication date: September 5, 2013
    Applicant: International Business Machines Corporation
    Inventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
  • Patent number: 8447583
    Abstract: A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
  • Patent number: 8428930
    Abstract: Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: April 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
  • Patent number: 8387031
    Abstract: A mechanism is provided for operating a computing system, in which an inner virtual machine translates first instructions, which are supported by the inner virtual machine, into second instructions, which are supported by an outer virtual machine. The mechanism encodes, in the inner virtual machine, third instructions into the second instructions into which the first instructions are translated, the third instructions including hints for facilitating an execution of the second instructions, and, in an event the hints are supported by the outer virtual machine, initiating the execution of the second instructions while utilizing the hints by the outer virtual machine to achieve an increased efficiency of the execution of the second instructions.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: February 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Derek B. Inglis, Marcel Mitran, Ali I. Sheikh, Kevin A. Stoodley