Patents by Inventor Ali I. Sheikh
Ali I. Sheikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10133652Abstract: Embodiments of the present invention provide a method, computer program product, and system for debugging optimized code. The system includes a FAT binary, wherein the FAT binary comprises a non-optimized native code and an internal representation of a program's source code. An optimus program is configured to transform the internal representation of the program's source code into a fully optimized native code. The system also includes an enhanced loader, wherein the enhanced loader is configured to communicate with a debugger to determine a type of code to load.Type: GrantFiled: September 15, 2017Date of Patent: November 20, 2018Assignee: International Business Machines CorporationInventors: Michael J. Moniz, Ali I. Sheikh, Diana P. Sutandie, Srivatsan Vijayakumar, Ying Di Zhang
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Patent number: 9940218Abstract: Embodiments of the present invention provide a method, computer program product, and system for debugging optimized code. The system includes a FAT binary, wherein the FAT binary comprises a non-optimized native code and an internal representation of a program's source code. An optimus program is configured to transform the internal representation of the program's source code into a fully optimized native code. The system also includes an enhanced loader, wherein the enhanced loader is configured to communicate with a debugger to determine a type of code to load.Type: GrantFiled: February 15, 2016Date of Patent: April 10, 2018Assignee: International Business Machines CorporationInventors: Michael J. Moniz, Ali I. Sheikh, Diana P. Sutandie, Srivatsan Vijayakumar, Ying Di Zhang
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Patent number: 9858054Abstract: A method for optimizing binary code in a language having access to binary coded decimal variable. The method includes: generating a first compiler expression of the binary code; analyzing a use-definition and/or a definition-use for the first compiler expression; generating a second compiler expression by identifying logical binary coded decimal (BCD) variables in the first compiler expression; assigning temporary variables to the logical BCD variables, wherein the second compiler expression includes packed decimal operations and the assigned temporary variables; and converting a packed decimal operation in the second compiler expression and an assigned temporary variable to a decimal floating point (DFP) if sign information and precision information are not lost during conversion from BCD to DFP, wherein identifying logical BCD variables includes: in the use-definition and/or definition-use of operands, regarding an operand of definition and an operand of use as the same logical BCD variables.Type: GrantFiled: February 5, 2016Date of Patent: January 2, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshihiko Koju, Ali I Sheikh
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Publication number: 20170371767Abstract: Embodiments of the present invention provide a method, computer program product, and system for debugging optimized code. The system includes a FAT binary, wherein the FAT binary comprises a non-optimized native code and an internal representation of a program's source code. An optimus program is configured to transform the internal representation of the program's source code into a fully optimized native code. The system also includes an enhanced loader, wherein the enhanced loader is configured to communicate with a debugger to determine a type of code to load.Type: ApplicationFiled: September 15, 2017Publication date: December 28, 2017Inventors: Michael J. Moniz, Ali I. Sheikh, Diana P. Sutandie, Srivatsan Vijayakumar, Ying Di Zhang
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Publication number: 20170235666Abstract: Embodiments of the present invention provide a method, computer program product, and system for debugging optimized code. The system includes a FAT binary, wherein the FAT binary comprises a non-optimized native code and an internal representation of a program's source code. An optimus program is configured to transform the internal representation of the program's source code into a fully optimized native code. The system also includes an enhanced loader, wherein the enhanced loader is configured to communicate with a debugger to determine a type of code to load.Type: ApplicationFiled: February 15, 2016Publication date: August 17, 2017Inventors: Michael J. Moniz, Ali I. Sheikh, Diana P. Sutandie, Srivatsan Vijayakumar, Ying Di Zhang
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Publication number: 20160154635Abstract: A method for optimizing binary code in a language having access to binary coded decimal variable. The method includes: generating a first compiler expression of the binary code; analyzing a use-definition and/or a definition-use for the first compiler expression; generating a second compiler expression by identifying logical binary coded decimal (BCD) variables in the first compiler expression; assigning temporary variables to the logical BCD variables, wherein the second compiler expression includes packed decimal operations and the assigned temporary variables; and converting a packed decimal operation in the second compiler expression and an assigned temporary variable to a decimal floating point (DFP) if sign information and precision information are not lost during conversion from BCD to DFP, wherein identifying logical BCD variables includes: in the use-definition and/or definition-use of operands, regarding an operand of definition and an operand of use as the same logical BCD variables.Type: ApplicationFiled: February 5, 2016Publication date: June 2, 2016Inventors: TOSHIHIKO KOJU, ALI I SHEIKH
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Patent number: 9280328Abstract: A method for optimizing binary code in a language having access to binary coded decimal variable. The method includes: generating a first compiler expression of the binary code; analyzing a use-definition and/or a definition-use for the first compiler expression; generating a second compiler expression by identifying logical binary coded decimal (BCD) variables in the first compiler expression; assigning temporary variables to the logical BCD variables, wherein the second compiler expression includes packed decimal operations and the assigned temporary variables; and converting a packed decimal operation in the second compiler expression and an assigned temporary variable to a decimal floating point (DFP) if sign information and precision information are not lost during conversion from BCD to DFP, wherein identifying logical BCD variables includes: in the use-definition and/or definition-use of operands, regarding an operand of definition and an operand of use as the same logical BCD variables.Type: GrantFiled: April 9, 2014Date of Patent: March 8, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshihiko Koju, Ali I Sheikh
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Patent number: 9158566Abstract: Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page.Type: GrantFiled: November 13, 2012Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Theodore J Bohizic, Reid T Copeland, Marcel Mitran, Ali I Sheikh
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Patent number: 8949106Abstract: A selected group of Guest machine instructions in an emulation environment are translated to a semantic routine of Host machine instructions, wherein Guest cells corresponding to an opcode portion of a Guest instruction are mapped to corresponding Host cells, wherein the semantic routine of Host machine instructions are patched into a Host cell corresponding to the first Guest cell of the group of Guest machine instructions, wherein other Host cells of the corresponding Host cells are patched with semantic routines for emulating single instructions associated with the corresponding Guest cell.Type: GrantFiled: September 18, 2009Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
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Publication number: 20140317608Abstract: A method for optimizing binary code in a language having access to binary coded decimal variable. The method includes: generating a first compiler expression of the binary code; analyzing a use-definition and/or a definition-use for the first compiler expression; generating a second compiler expression by identifying logical binary coded decimal (BCD) variables in the first compiler expression; assigning temporary variables to the logical BCD variables, wherein the second compiler expression includes packed decimal operations and the assigned temporary variables; and converting a packed decimal operation in the second compiler expression and an assigned temporary variable to a decimal floating point (DFP) if sign information and precision information are not lost during conversion from BCD to DFP, wherein identifying logical BCD variables includes: in the use-definition and/or definition-use of operands, regarding an operand of definition and an operand of use as the same logical BCD variables.Type: ApplicationFiled: April 9, 2014Publication date: October 23, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshihiko Koju, Ali I. Sheikh
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Patent number: 8869128Abstract: A method, program, and apparatus for optimizing compiled code using a dynamic compiler. The method includes the steps of: generating intermediate code from a trace, which is an instruction sequence described in machine language; computing an offset between an address value, which is a base point of an indirect branch instruction, and a start address of a memory page, which includes a virtual address referred to by the information processing apparatus immediately after processing a first instruction; determining whether an indirect branch instruction that is subsequent to the first instruction causes processing to jump to another memory page, by using a value obtained from adding the offset to a displacement made by the indirect branch instruction; and optimizing the intermediate code by using the result of the determining step.Type: GrantFiled: January 31, 2013Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: Toshihiko Koju, Ali I Sheikh, Xin Tong
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Patent number: 8819647Abstract: Nested virtual machines cooperate with one another to improve system performance. In particular, an outer virtual machine performs tasks on behalf of an inner virtual machine to improve system performance. One such task includes translation of instructions for the inner virtual machine.Type: GrantFiled: January 25, 2008Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Marcel Mitran, Ali I. Sheikh
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Patent number: 8768683Abstract: A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed.Type: GrantFiled: April 19, 2013Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Theodore J Bohizic, Reid T Copeland, Marcel Mitran, Ali I Sheikh
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Publication number: 20140136179Abstract: Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page.Type: ApplicationFiled: November 13, 2012Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodore J Bohizic, Reid T Copeland, Marcel Mitran, Ali I Sheikh
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Patent number: 8713289Abstract: Emulation of source machine instructions is provided in which target machine CPU condition codes are employed to produce emulated condition code settings without the use, encoding or generation of branching instructions.Type: GrantFiled: January 30, 2007Date of Patent: April 29, 2014Assignee: International Business Machines CorporationInventors: Reid T. Copeland, Patrick R. Doyle, Charles B. Hall, Andrew Johnson, Ali I. Sheikh
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Patent number: 8689198Abstract: A compiling system and method for optimizing binary code. The method includes the step of replacing a memory access on a stack area in order to save a value of a register with local variable access. The method further includes: giving a call number to a call instruction and an inlined code in response to an inline expansion of a code to be called by the call instruction; creating a parent-child relationship information for at least one of the call number; processing the memory accesses with an escaped stack pointer as a base address if a stack pointer has escaped; prohibiting a replacement of a prohibited memory access if the stack pointer has escaped; and replacing unprohibited memory access with the local variable access if the stack pointer has escaped.Type: GrantFiled: August 10, 2011Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Motohiro Kawahito, Ali I. Sheikh, Vijay Sundaresan
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Publication number: 20130231913Abstract: A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction.Type: ApplicationFiled: April 19, 2013Publication date: September 5, 2013Applicant: International Business Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
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Patent number: 8447583Abstract: A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed.Type: GrantFiled: September 18, 2009Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
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Patent number: 8428930Abstract: Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page.Type: GrantFiled: September 18, 2009Date of Patent: April 23, 2013Assignee: International Business Machines CorporationInventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
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Patent number: 8387031Abstract: A mechanism is provided for operating a computing system, in which an inner virtual machine translates first instructions, which are supported by the inner virtual machine, into second instructions, which are supported by an outer virtual machine. The mechanism encodes, in the inner virtual machine, third instructions into the second instructions into which the first instructions are translated, the third instructions including hints for facilitating an execution of the second instructions, and, in an event the hints are supported by the outer virtual machine, initiating the execution of the second instructions while utilizing the hints by the outer virtual machine to achieve an increased efficiency of the execution of the second instructions.Type: GrantFiled: January 23, 2009Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventors: Derek B. Inglis, Marcel Mitran, Ali I. Sheikh, Kevin A. Stoodley