Patents by Inventor Ali Icel

Ali Icel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11387364
    Abstract: A transistor includes a semiconductor substrate, a first source/drain region and a second source/drain region in the semiconductor substrate with a channel region between the source/drain regions, and a gate over the channel region. In addition, the transistor includes a first phase transition material (PTM) region between the first source/drain region and the channel region, and a second PTM region between the second source/drain region and the channel region. The PTM regions provide the transistor with improved off-state current (IOFF) without affecting the on-state current (ION), and thus an improved ION/IOFF ratio. The transition threshold of PTM regions from dielectric to conductor can be customized based on, for example, PTM material type, doping therein, and/or strain therein.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: July 12, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Avinash Lahgere, Prashanth Paramahans Manik, Peter Javorka, Ali Icel, Mohit Bajaj
  • Publication number: 20220140131
    Abstract: A transistor includes a semiconductor substrate, a first source/drain region and a second source/drain region in the semiconductor substrate with a channel region between the source/drain regions, and a gate over the channel region. In addition, the transistor includes a first phase transition material (PTM) region between the first source/drain region and the channel region, and a second PTM region between the second source/drain region and the channel region. The PTM regions provide the transistor with improved off-state current (IOFF) without affecting the on-state current (ION), and thus an improved ION/IOFF ratio. The transition threshold of PTM regions from dielectric to conductor can be customized based on, for example, PTM material type, doping therein, and/or strain therein.
    Type: Application
    Filed: November 3, 2020
    Publication date: May 5, 2022
    Inventors: Avinash Lahgere, Prashanth Paramahans Manik, Peter Javorka, Ali Icel, Mohit Bajaj
  • Patent number: 7986008
    Abstract: SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of a first conductivity type and first doping concentration in the first semiconductor layer. A channel region of a second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of the first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of the first conductivity determining dopant.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: July 26, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ali Icel, Qiang Chen, Mario M. Pelella
  • Patent number: 7844927
    Abstract: According to one exemplary embodiment, a method for producing a quality assured semiconductor device model when at least one critical parameter of a semiconductor device process is upgraded includes verifying the quality assured semiconductor device model for consistency against measured data or projected targets. The method further includes verifying the quality assured semiconductor device model for accuracy and consistency when one of a number of critical parameters is varied. The method further includes verifying consistency of the quality assured semiconductor device model against an old semiconductor device model. The method further includes verifying the quality assured semiconductor device model over a range of each of a number of semiconductor device dependencies. The method further includes verifying the quality assured semiconductor device model for digital circuit operation. The method further includes verifying the quality assured semiconductor device model for analog circuit operation.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: November 30, 2010
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Zhi-Yuan Wu, Ali Icel, Judy X. An, Ciby T. Thuruthiyil
  • Publication number: 20090184372
    Abstract: SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of a first conductivity type and first doping concentration in the first semiconductor layer. A channel region of a second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of the first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of the first conductivity determining dopant.
    Type: Application
    Filed: March 27, 2009
    Publication date: July 23, 2009
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Ali ICEL, Qiang CHEN, Mario M. PELELLA
  • Patent number: 7531403
    Abstract: SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of first conductivity type and first doping concentration in the first semiconductor layer. A channel region of second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of first conductivity determining dopant.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: May 12, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ali Icel, Qiang Chen, Mario M. Pelella
  • Publication number: 20080177523
    Abstract: According to one exemplary embodiment, a method for producing a quality assured semiconductor device model when at least one critical parameter of a semiconductor device process is upgraded includes verifying the quality assured semiconductor device model for consistency against measured data or projected targets. The method further includes verifying the quality assured semiconductor device model for accuracy and consistency when one of a number of critical parameters is varied. The method further includes verifying consistency of the quality assured semiconductor device model against an old semiconductor device model. The method further includes verifying the quality assured semiconductor device model over a range of each of a number of semiconductor device dependencies. The method further includes verifying the quality assured semiconductor device model for digital circuit operation. The method further includes verifying the quality assured semiconductor device model for analog circuit operation.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 24, 2008
    Inventors: Zhi-Yuan Wu, Ali Icel, Judy X. An, Ciby T. Thuruthiyil
  • Publication number: 20080079074
    Abstract: SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of first conductivity type and first doping concentration in the first semiconductor layer. A channel region of second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of first conductivity determining dopant.
    Type: Application
    Filed: October 2, 2006
    Publication date: April 3, 2008
    Inventors: Ali Icel, Qiang Chen, Mario M. Pelella