Patents by Inventor Ali Keshavarzi
Ali Keshavarzi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230197723Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: ApplicationFiled: February 13, 2023Publication date: June 22, 2023Inventors: Ali KESHAVARZI, Ta-Pen GUO, Shu-Hui SUNG, Hsiang-Jen TSENG, Shyue-Shyh LIN, Lee-Chung LU, Chung-Cheng WU, Li-Chun TIEN, Jung-Chan YANG, Ting Yu CHEN, Min CAO, Yung-Chin HOU
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Patent number: 11581314Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: GrantFiled: December 20, 2019Date of Patent: February 14, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ali Keshavarzi, Ta-Pen Guo, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin, Lee-Chung Lu, Chung-Cheng Wu, Li-Chun Tien, Jung-Chan Yang, Ting Yu Chen, Min Cao, Yung-Chin Hou
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Publication number: 20210074821Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.Type: ApplicationFiled: September 21, 2020Publication date: March 11, 2021Inventors: Krishnaswamy Ramkumar, Igor Kouznetsov, Venkatraman Prabhakar, Ali Keshavarzi
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Patent number: 10784356Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.Type: GrantFiled: August 8, 2018Date of Patent: September 22, 2020Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Krishnaswamy Ramkumar, Igor Kouznetsov, Venkatraman Prabhakar, Ali Keshavarzi
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Publication number: 20200126986Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: ApplicationFiled: December 20, 2019Publication date: April 23, 2020Inventors: Ali KESHAVARZI, Ta-Pen GUO, Shu-Hui SUNG, Hsiang-Jen TSENG, Shyue-Shyh LIN, Lee-Chung LU, Chung-Cheng WU, Li-Chun TIEN, Jung-Chan YANG, Ting-Yu CHEN, Min CAO, Yung-Chin HOU
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Publication number: 20200051642Abstract: A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell has a memory transistor including an angled lightly doped drain (LDD) implant, and a select transistor including a shared source region with a halo implant. The flash memory portion and the EEPROM portion are disposed within one single semiconductor die. Other embodiments are also disclosed.Type: ApplicationFiled: June 24, 2019Publication date: February 13, 2020Inventors: Gary Menezes, Krishnaswamy Ramkumar, Ali Keshavarzi, Venkatraman Prabhakar
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Patent number: 10535655Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: GrantFiled: April 8, 2016Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ali Keshavarzi, Ta-Pen Guo, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin, Lee-Chung Lu, Chung-Cheng Wu, Li-Chun Tien, Jung-Chan Yang, Ting-Yu Chen, Min Cao, Yung-Chin Hou
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Patent number: 10332599Abstract: A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell has a memory transistor including an angled lightly doped drain (LDD) implant, and a select transistor including a shared source region with a halo implant. The flash memory portion and the EEPROM portion are disposed within one single semiconductor die. Other embodiments are also disclosed.Type: GrantFiled: March 12, 2018Date of Patent: June 25, 2019Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Gary Menezes, Krishnaswamy Ramkumar, Ali Keshavarzi, Venkatraman Prabhakar
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Publication number: 20190147960Abstract: A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell has a memory transistor including an angled lightly doped drain (LDD) implant, and a select transistor including a shared source region with a halo implant. The flash memory portion and the EEPROM portion are disposed within one single semiconductor die. Other embodiments are also disclosed.Type: ApplicationFiled: March 12, 2018Publication date: May 16, 2019Applicant: Cypress Semiconductor CorporationInventors: Gary Menezes, Krishnaswamy Ramkumar, Ali Keshavarzi, Venkatraman Prabhakar
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Publication number: 20190088487Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.Type: ApplicationFiled: August 8, 2018Publication date: March 21, 2019Applicant: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Igor Kouznetsov, Venkatraman Prabhakar, Ali Keshavarzi
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Patent number: 10062573Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.Type: GrantFiled: August 22, 2017Date of Patent: August 28, 2018Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Igor Kouznetsov, Venkatraman Prabhakar, Ali Keshavarzi
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Patent number: 9624094Abstract: A microelectronic system including hydrogen barriers and copper pillars for wafer level packaging and method of fabricating the same are provided. Generally, the method includes: forming an insulating hydrogen barrier over a surface of a first chip; exposing at least a portion of an electrical contact electrically coupled to a component in the first chip by removing a portion of the insulating hydrogen barrier, the component including a material susceptible to degradation by hydrogen; forming a conducting hydrogen barrier over at least the exposed portion of the electrical contact; and forming a copper pillar over the conducting hydrogen barrier. In one embodiment, the material susceptible to degradation is lead zirconate titanate (PZT) and the microelectronic systems device is a ferroelectric random access memory including a ferroelectric capacitor with a PZT ferroelectric layer. Other embodiments are also disclosed.Type: GrantFiled: April 1, 2016Date of Patent: April 18, 2017Assignee: Cypress Semiconductor CorporationInventors: Shan Sun, Ali Keshavarzi, Thomas Davenport, Thurman John Rodgers
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Publication number: 20160372469Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: ApplicationFiled: April 8, 2016Publication date: December 22, 2016Inventors: Ali Keshavarzi, Ta-Pen Guo, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin, Lee-Chung Lu, Chung-Cheng Wu, Li-Chun Tien, Jung-Chan Yang, Ting-Yu Chen, Min Cao, Yung-Chin Hou
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Patent number: 9385213Abstract: A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region.Type: GrantFiled: December 20, 2012Date of Patent: July 5, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Cheng Wu, Ali Keshavarzi, Ka Hing Fung, Ta-Pen Guo, Jiann-Tyng Tzeng, Yen-Ming Chen, Shyue-Shyh Lin, Shyh-Wei Wang, Sheng-Jier Yang, Hsiang-Jen Tseng, David B. Scott, Min Cao
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Patent number: 9312260Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.Type: GrantFiled: April 13, 2011Date of Patent: April 12, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ali Keshavarzi, Ta-Pen Guo, Helen Shu-Hui Chang, Hsiang-Jen Tseng, Shyue-Shyh Lin, Lee-Chung Lu, Chung-Cheng Wu, Li-Chun Tien, Jung-Chan Yang, Shu-Min Chen, Min Cao, Yung-Chin Hou
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Patent number: 8962421Abstract: A method for fabricating a FinFET integrated circuit includes depositing a first polysilicon layer at a first end of a diffusion region and a second polysilicon layer at a second end of the diffusion region; diffusing an n-type material into the diffusion region to form a diffused resistor; and epitaxially growing a silicon material between the first and second polysilicon layers to form fins structures over the diffused resistor and spanning between the first and second polysilicon layers.Type: GrantFiled: November 15, 2012Date of Patent: February 24, 2015Assignee: GLOBALFOUNDRIES, Inc.Inventors: Gopal Srinivasan, Andy Wei, Dinesh Somasekhar, Ali Keshavarzi, Subi Kengeri
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Publication number: 20140134822Abstract: A method for fabricating a FinFET integrated circuit includes depositing a first polysilicon layer at a first end of a diffusion region and a second polysilicon layer at a second end of the diffusion region; diffusing an n-type material into the diffusion region to form a diffused resistor; and epitaxially growing a silicon material between the first and second polysilicon layers to form fins structures over the diffused resistor and spanning between the first and second polysilicon layers.Type: ApplicationFiled: November 15, 2012Publication date: May 15, 2014Applicant: GLOBALFOUNDRIES, INC.Inventors: Gopal Srinivasan, Andy Wei, Dinesh Somasekhar, Ali Keshavarzi, Subi Kengeri
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Patent number: 8689154Abstract: An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.Type: GrantFiled: April 13, 2012Date of Patent: April 1, 2014Assignee: GlobalFoundries Inc.Inventors: Mahbub Rashed, David Doman, Dinesh Somasekhar, Yan Wang, Yunfei Deng, Navneet Jain, Jongwook Kye, Ali Keshavarzi, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20130275935Abstract: An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.Type: ApplicationFiled: April 13, 2012Publication date: October 17, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Mahbub Rashed, David Doman, Dinesh Somasekhar, Yan Wang, Yunfei Deng, Navneet Jain, Jongwook Kye, Ali Keshavarzi, Subramani Kengeri, Suresh Venkatesan
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Patent number: 8513741Abstract: In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.Type: GrantFiled: August 23, 2011Date of Patent: August 20, 2013Assignee: Intel CorporationInventors: Ali Keshavarzi, Juanita Kurtin, Vivek De