Patents by Inventor Ali M. El-Husseini

Ali M. El-Husseini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11183226
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Publication number: 20210082481
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Applicant: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Patent number: 10854249
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Publication number: 20200327914
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Application
    Filed: June 27, 2020
    Publication date: October 15, 2020
    Applicant: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Patent number: 10706900
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Publication number: 20200143853
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 7, 2020
    Applicant: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini