Abstract: Circuits, methods, and apparatus for transmitting, receiving, aligning and re-synchronizing high-speed single-ended signals by aligning a clock signal to one or more received data signals. A receiver amplifier circuit senses and captures low swing single ended signals at the receiver. Alignment is done on a per pin basis where a clock signal is distributed and independently phase shifted and aligned to each incoming data signal. In one example, a preamble containing a training data pattern is transmitted. The receiver steps through a number of dynamic timing alignment codes, each of which selects a different phase-shifted clock signal. The received data is examined for errors and the optimal clock signal is selected. Periodic dynamic readjustments of multiple clock alignment circuits may be made to compensate for temperature and voltage drift and variations.

Abstract: Circuits, methods, and apparatus that provide accurate on-chip termination impedances for high-speed data interface circuits. One embodiment of the present invention provides a series termination impedance for an output driver as well as shunt termination impedances for a receive circuit. These impedances are dynamically adjusted to match a ratio of an external precision resistor. Multiple coarse and fine-grain adjustments are automatically performed by the hardware. Adjustment may occur at power up or at programmable periodic intervals, and one or both of the impedances may be updated each time an interface begins to transmit or receive data. A specific embodiment utilizes a reference resistance that is made up of a parallel combination of resistors connected through MOS transistors. This resistance is adjusted by connecting or disconnecting the parallel resistors until it matches a ratio of an external resistor.

Abstract: A programmable input/output buffer has a first plurality of pull-down transistors connected between a supply voltage and an electrical system conductor on the integrated circuit and a second plurality of pull-down transistors connected between the electrical conductor and the system reference voltage. Reference circuits generate signals to turn on a first number of said first plurality of pull-up transistors and/or a second number of said second plurality of pull-down transistors to provide an input/output buffer impedance matching the impedance of the external transmission line either sending a signal to the programmable input/output buffer or receiving a signal from the programmable input/output buffer.

Abstract: A programmable input/output buffer has a first plurality of pull-down transistors connected between a supply voltage and an electrical system conductor on the integrated circuit and a second plurality of pull-down transistors connected between the electrical conductor and the system reference voltage. Reference circuits generate signals to turn on a first number of said first plurality of pull-up transistors and/or a second number of said second plurality of pull-down transistors to provide an input/output buffer impedance matching the impedance of the external transmission line either sending a signal to the programmable input/output buffer or receiving a signal from the programmable input/output buffer.

Abstract: DRAM with column slices improves circuit redundancy. Slices have global column length, and memory is divided in groups with size of redundancy columns having slices. Failure detected among slices of corresponding storage is replaced by corresponding redundancy column slice, such that column redundancy division is in vertical column direction. Column includes global data line shared by column slices and multiple blocks. Redundant column is added to memory array, and redundant control circuits or comparator are proximate to data sense amplifiers. Defective column address are provided to controller through non-volatile memory, or laser-blown or electrically-programmable fuses. When column address is presented, incoming address is compared with stored address, such that select data is output on redundant data line when equal addresses (i.e., hit detect), or normal data is output when unequal addresses (i.e., "miss" detected).

Abstract: A method and apparatus for reading and writing data into a random access memory array having a dummy bit. The method includes the steps of providing a clock signal having two edges, one going from low to high and the other going from high to low. The edge going to high from low triggers an enable signal. The enable signal substantially simultaneously triggers a main wordline signal and a dummy wordline signal, the main wordline signal initiating a memory access process while the dummy wordline signal causes the generation of a dummy bit signal from the dummy bit, the combination of the main wordline signal and the dummy bit signal permitting memory access. The dummy bit signal shuts off the enable signal, which in turn causes the memory access process to be terminated and the memory array to go into a bit line precharging stage in preparation for a next read or write cycle, whereby bit line precharging may be commenced prior to the end of the clock cycle.