Patents by Inventor Ali Nazemi
Ali Nazemi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9197214Abstract: A high speed level shifter interfaces a high speed DAC to the digital information that the DAC processes. The level shifter may convert CMOS level digital representations to, for example, CML level digital representations for processing by the DAC. The level shifter conserves the voltage swing in the CMOS level representations (e.g., about 1V). The level shifter also avoids voltage overstress, using a feedback loop to constrain the voltage amplitude, and thereby facilitates the use of fast thin film transistors in its architecture.Type: GrantFiled: September 12, 2013Date of Patent: November 24, 2015Assignee: Broadcom CorporationInventors: Ali Nazemi, Kangmin Hu, Jun Cao, Afshin Doctor Momtaz
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Patent number: 9136904Abstract: Embodiments of the present disclosure enable bandwidth extension of receiver front-end circuits without the use of inductors. As a result, significantly smaller and cheaper receiver implementations are made possible. In an embodiment, bandwidth extension is achieved by virtue of very small floating capacitors that are coupled around amplifier stages of the receiver front-end circuit. Each of the capacitors is configured to generate a negative capacitance for the preceding stage (e.g., equalizer or amplifier), thus extending the bandwidth of the preceding stage. A capacitively-degenerated cross-coupled transistor pair allows bandwidth extension for the final (e.g., amplifier) stage. Embodiments further enable DC offset compensation with the use of a digital feedback loop. The feedback loop can thus be turned on/off as needed, reducing power consumption.Type: GrantFiled: August 6, 2012Date of Patent: September 15, 2015Assignee: Broadcom CorporationInventors: Tamer Ali, Ali Nazemi, Namik Kocaman
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Publication number: 20150180649Abstract: A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.Type: ApplicationFiled: March 3, 2015Publication date: June 25, 2015Inventors: Mahmoud Reza AHMADI, Siavash FALLAHI, Tamer ALI, Ali NAZEMI, Hassan MAAREFI, Burak CATLI, Afshin MOMTAZ
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Patent number: 9001869Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.Type: GrantFiled: July 19, 2013Date of Patent: April 7, 2015Assignee: Broadcom CorporationInventors: Mahmoud Reza Ahmadi, Siavash Fallahi, Tamer Ali, Ali Nazemi, Hassan Maarefi, Burak Catli, Afshin Momtaz
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Patent number: 8958501Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.Type: GrantFiled: December 19, 2012Date of Patent: February 17, 2015Assignee: Broadcom CorporationInventors: Ali Nazemi, Mahmoud Reza Ahmadi, Tamer Ali, Bo Zhang, Mohammed Abdul-Latif, Namik Kocaman, Afshin Momtaz
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Publication number: 20150035563Abstract: A high speed level shifter interfaces a high speed DAC to the digital information that the DAC processes. The level shifter may convert CMOS level digital representations to, for example, CML level digital representations for processing by the DAC. The level shifter conserves the voltage swing in the CMOS level representations (e.g., about 1V). The level shifter also avoids voltage overstress, using a feedback loop to constrain the voltage amplitude, and thereby facilitates the use of fast thin film transistors in its architecture.Type: ApplicationFiled: September 12, 2013Publication date: February 5, 2015Applicant: Broadcom CorporationInventors: Ali Nazemi, Kangmin Hu, Jun Cao, Afshin Doctor Momtaz
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Patent number: 8836553Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.Type: GrantFiled: January 30, 2013Date of Patent: September 16, 2014Assignee: Broadcom CorporationInventors: Bo Zhang, Ali Nazemi, Mahmoud Reza Ahmadi, Afshin Momtaz, Heng Zhang, Hassan Maarefi
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Publication number: 20140241442Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.Type: ApplicationFiled: July 19, 2013Publication date: August 28, 2014Inventors: Mahmoud Reza Ahmadi, Siavash Fallahi, Tamer Ali, Ali Nazemi, Hassan Maarefi, Burak Catli, Afshin Momtaz
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Publication number: 20140146922Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.Type: ApplicationFiled: December 19, 2012Publication date: May 29, 2014Applicant: BROADCOM CORPORATIONInventors: Ali Nazemi, Mahmoud Reza Ahmadi, Tamer Ali, Bo Zhang, Mohammed Abdul-Latif, Namik Kocaman, Afshin Momtaz
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Publication number: 20140104086Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.Type: ApplicationFiled: January 30, 2013Publication date: April 17, 2014Applicant: Broadcom CorporationInventors: Bo Zhang, Ali Nazemi, Mahmoud Reza Ahmadi, Afshin Momtaz, Heng Zhang, Hassan Maarefi
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Patent number: 8664973Abstract: Embodiments of the present disclosure provide input termination circuits that overcome the deficiencies of conventional designs. Specifically, embodiments eliminate large-on chip bypass capacitors that are commonly used for common mode termination, and instead use an active capacitor-multiplier (C-multiplier) circuit at the common mode node. The C-multiplier circuit mimics a large capacitor at high frequency. By eliminating large on-chip bypass capacitors, the IC design (e.g., receiver) is reduced in size, without affecting common mode return loss performance. Embodiments may be used with any applications that require input termination, and particularly with differential applications that require common mode termination.Type: GrantFiled: August 6, 2012Date of Patent: March 4, 2014Assignee: Broadcom CorporationInventors: Tamer Ali, Ali Nazemi
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Publication number: 20140035696Abstract: Embodiments of the present disclosure provide input termination circuits that overcome the deficiencies of conventional designs. Specifically, embodiments eliminate large-on chip bypass capacitors that are commonly used for common mode termination, and instead use an active capacitor-multiplier (C-multiplier) circuit at the common mode node. The C-multiplier circuit mimics a large capacitor at high frequency. By eliminating large on-chip bypass capacitors, the IC design (e.g., receiver) is reduced in size, without affecting common mode return loss performance. Embodiments may be used with any applications that require input termination, and particularly with differential applications that require common mode termination.Type: ApplicationFiled: August 6, 2012Publication date: February 6, 2014Applicant: Broadcom CorporationInventors: Tamer ALI, Ali Nazemi
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Publication number: 20140036982Abstract: Embodiments of the present disclosure enable bandwidth extension of receiver front-end circuits without the use of inductors. As a result, significantly smaller and cheaper receiver implementations are made possible. In an embodiment, bandwidth extension is achieved by virtue of very small floating capacitors that are coupled around amplifier stages of the receiver front-end circuit. Each of the capacitors is configured to generate a negative capacitance for the preceding stage (e.g., equalizer or amplifier), thus extending the bandwidth of the preceding stage. A capacitively-degenerated cross-coupled transistor pair allows bandwidth extension for the final (e.g., amplifier) stage. Embodiments further enable DC offset compensation with the use of a digital feedback loop. The feedback loop can thus be turned on/off as needed, reducing power consumption.Type: ApplicationFiled: August 6, 2012Publication date: February 6, 2014Applicant: Broadcom CorporationInventors: Tamer ALI, Ali Nazemi, Namik Kocaman
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Patent number: 8618835Abstract: An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal.Type: GrantFiled: September 23, 2011Date of Patent: December 31, 2013Assignee: Broadcom CorporationInventors: Burak Catli, Ali Nazemi, Mahmoud Reza Ahmadi, Ullas Singh, Jun Cao, Afshin Momtaz
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Publication number: 20130076394Abstract: An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: Broadcom CorporationInventors: Burak Catli, Ali Nazemi, Mahmoud Reza Ahmadi, Ullas Singh, Jun Cao, Afshin Momtaz
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Patent number: 8094056Abstract: A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.Type: GrantFiled: September 15, 2008Date of Patent: January 10, 2012Assignee: Clariphy Communications, Inc.Inventors: Ali Nazemi, Georgios Asmanis, German Cesar Augusto Luna, Mahyar Kargar, Carl Grace, Sumant Ramprasad
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Patent number: 7808417Abstract: A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.Type: GrantFiled: September 15, 2008Date of Patent: October 5, 2010Assignee: ClariPhy Communications, Inc.Inventor: Ali Nazemi
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Publication number: 20090243907Abstract: A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.Type: ApplicationFiled: September 15, 2008Publication date: October 1, 2009Inventors: Ali Nazemi, Georgios Asmanis, German Luna, Mahyar Kargar, Carl Grace, Sumant Ramprasad
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Publication number: 20090096647Abstract: A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.Type: ApplicationFiled: September 15, 2008Publication date: April 16, 2009Inventor: Ali Nazemi