Abstract: A direct memory access (“DMA”) request specifies a target address within an input/output virtual address (“IOVA”) space. The DMA target is validated and data are transferred between the target identified by the IOVA and a second location. Chipsets and systems using embodiments of the invention are also described and claimed.

Abstract: Provided are techniques for writing doorbell information. In accordance with certain techniques, one or more protection domains are created. One or more data structures are created, wherein each of the data structures is associated with at least one protection domain. One of the data structures is updated. A doorbell structure address for a doorbell structure associated with the updated data structure is computed. Doorbell information is written at the computed doorbell structure address. In accordance with certain other techniques, doorbell information is received. A doorbell structure address is decoded from the doorbell information. A first protection domain identifier is determined from the doorbell structure address. A resource context of a data structure is determined from the doorbell information. The resource context at the doorbell address is read to determine a second protection domain identifier.

Abstract: In one embodiment, a method is provided. The method of this embodiment provides determining if a management queue can be created, and if a management queue can be created, allocating virtually contiguous memory to a management queue associated with a device, registering the management queue, and creating a management queue context.

Abstract: Provided are a method, system, and program for utilizing a virtualized data structure table such as an address translation and protection table (TPT), for example, in an I/O device. The virtualized data structure table has virtually contiguous data structures but not necessarily physically contiguous data structures in system memory. The data structure table may be accessed in a virtually contiguous manner. In the illustrated embodiment, the table is subdivided at a first hierarchal level into a plurality of virtually contiguous units or segments. Each unit or segment is in turn subdivided at a second hierarchal level into a plurality of virtually contiguous subunits, subsegments, pages or blocks. Each page or block is in turn subdivided at a third hierarchal level into a plurality of physically contiguous table entries.

Abstract: Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a state of an event data structure. The Input/Output device writes an event entry into the event data structure in response to determining that the event has occurred. After writing the event entry, the Input/Output device determines whether to generate an interrupt or not based on the state of the event data structure. Additionally provided are techniques for interrupt processing in which an I/O device driver determines that an interrupt has occurred. The I/O device driver reads an event entry in an event data structure in response to determining that the interrupt has occurred. The I/O device driver updates a state of a structure state indicator to enable/disable interrupts.

Abstract: In one embodiment, the present invention includes a method to receive a data sequence in a receiver having a plurality of lanes, detect a predetermined character in the data sequence in a first lane, and track a time period until the plurality of lanes detects the predetermined character.