Abstract: This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.

Abstract: A switch current sensor includes a summing circuit, at least one first-type switch current sensor subcircuit and configured to be coupled at a first input to a conductor, and coupled at a first output to the summing circuit, and at least one second-type switch current sensor subcircuit configured to be coupled at a second input to the conductor and coupled at a second output to the summing circuit. The summing circuit is configured to aggregate the first output of the at least one first-type switch current sensor subcircuit and the second output of the at least one second-type switch current sensor subcircuit to obtain a voltage waveform that is proportional to a switch current configured to flow in the conductor, the voltage waveform including a DC component and steady-state AC components of the switch current.

Abstract: Driver circuits for a low-cost two-phase motor are disclosed. Cost reductions may be further achieved by utilizing a printed circuit board (PCB)-based stator and methods of manufacturing, as disclosed herein. The disclosed technology can be particularly well matched for use in two-phase motors, such as axial-flux motors the utilize one or more ferrite-based rotors and a printed circuit board (PCB)-based stator. In certain implementations, part or all of the motor driver circuitry may be integrated onto the same PCB as is utilized to define the stator windings. In other implementations, the motor driver circuitry may be independently utilized with other traditional electrical motors.

Abstract: In some source degeneration-based cascode LNAs, a cascode transistor may contribute a large portion of noise at mmWave frequencies due to lower output impedance from a bottom transistor (e.g., amplifying transistor or transconductance transistor) of the cascode. The cascode noise may negatively impact performance of the LNA. A first inductor (e.g., cascode inductor) may be coupled to the source of the cascode transistor and a second inductor (e.g., notch inductor) may be coupled to the gate of the bottom transistor such that the cascode inductor and a notch inductor inductively couple to each other, introducing a reverse-transmission zero in-band to reduce or eliminate cascode noise contribution and neutralize gate-drain capacitance of the bottom transistor with minimal area consumption.

Abstract: An electronic device may include wireless circuitry with a baseband processor, a transceiver, and an antenna. The transceiver may include a transmit path, a receive path, and a loopback path that couples the transmit path to the receive path. A passive all-pass filter may be interposed on the loopback path. Control circuitry may calibrate I/Q mismatch of the wireless circuitry using the all-pass filter to optimize the radio-frequency performance of the wireless circuitry. Performing I/Q mismatch calibration using the all-pass filter may serve to minimize area consumption in the transceiver, may minimize calibration time, and may allow for calibration over a relatively wide bandwidth.

Abstract: An electronic device may include wireless circuitry with a baseband processor, a transceiver, and an antenna. The transceiver may include a transmit path, a receive path, and a loopback path that couples the transmit path to the receive path. A passive all-pass filter may be interposed on the loopback path. Control circuitry may calibrate I/Q mismatch of the wireless circuitry using the all-pass filter to optimize the radio-frequency performance of the wireless circuitry. Performing I/Q mismatch calibration using the all-pass filter may serve to minimize area consumption in the transceiver, may minimize calibration time, and may allow for calibration over a relatively wide bandwidth.

Abstract: This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.

Abstract: This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.

Abstract: This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.

Abstract: An electronic device may include wireless circuitry with a baseband processor, a transceiver, and an antenna. The transceiver may include a transmit path, a receive path, and a loopback path that couples the transmit path to the receive path. A passive all-pass filter may be interposed on the loopback path. Control circuitry may calibrate I/Q mismatch of the wireless circuitry using the all-pass filter to optimize the radio-frequency performance of the wireless circuitry. Performing I/Q mismatch calibration using the all-pass filter may serve to minimize area consumption in the transceiver, may minimize calibration time, and may allow for calibration over a relatively wide bandwidth.

Abstract: An electronic device may include wireless circuitry with a baseband processor, a transceiver, and an antenna. The transceiver may include a transmit path, a receive path, and a loopback path that couples the transmit path to the receive path. A passive all-pass filter may be interposed on the loopback path. Control circuitry may calibrate I/Q mismatch of the wireless circuitry using the all-pass filter to optimize the radio-frequency performance of the wireless circuitry. Performing I/Q mismatch calibration using the all-pass filter may serve to minimize area consumption in the transceiver, may minimize calibration time, and may allow for calibration over a relatively wide bandwidth.

Abstract: An electronic device may include wireless circuitry with a baseband processor, a transceiver, and an antenna. The transceiver may include a transmit path, a receive path, and a loopback path that couples the transmit path to the receive path. A passive all-pass filter may be interposed on the loopback path. Control circuitry may calibrate I/Q mismatch of the wireless circuitry using the all-pass filter to optimize the radio-frequency performance of the wireless circuitry. Performing I/Q mismatch calibration using the all-pass filter may serve to minimize area consumption in the transceiver, may minimize calibration time, and may allow for calibration over a relatively wide bandwidth.

Abstract: A system and method of optimising supply networks comprises the method steps of i) receiving a resource request from a user; ii) assessing the requirements of the request; iii) identifying all potential resources within a database that would fulfil the requirements; iv) ranking the potential resources in order of preference; v) allocating the most preferable resource to fulfil the request; and wherein, in the step of identifying all potential resources that would fulfil the requirements, all resource that does not fulfil primary requirements is discarded.

Abstract: Systems and method provided herein relate to reducing distortion of signals introduced by components on a phase path of a radio frequency system polar architecture. To reduce phase path distortion, a pre-distortion is introduced prior to a distortion caused by the components on the phase path. The pre-distortion in conjunction with the component distortion results in a transmission signal that forms its expected shape.

Abstract: Systems and method provided herein relate to reducing distortion of signals introduced by components on a phase path of a radio frequency system polar architecture. To reduce phase path distortion, a pre-distortion is introduced prior to a distortion caused by the components on the phase path. The pre-distortion in conjunction with the component distortion results in a transmission signal that forms its expected shape.

Abstract: Systems and method for improving operation of a radio frequency system are provided. One embodiment provides a radio frequency system that includes an amplifier device with a first data path and a second data path. Additionally, the radio frequency system includes a controller that instructs the radio frequency system to transmit a calibration signal, which includes a first portion that excites the first data path and a second portion that excites the second data path; determines time skew between the first and second data paths based at least in part on phase shift between a first sample of a feedback signal and the first portion, phase shift between a second sample of the feedback signal and the second portion, or both; and instructs the radio frequency system to adjust delay applied on the first data path, the second data path, or both based at least on the time skew.

Abstract: A quadrature modulator and a method of calibrating same by applying a first test tone signal to an in-phase modulation branch input of the modulator and a ninety degree phase-shifted version of the first test tone signal to a quadrature modulation branch input of the modulator. The carrier leakage level in an output signal of the modulator is measured and in response base band dc offset voltages are adjusted to minimize the carrier leakage. A second test tone signal is applied to the in-phase modulation branch input and a ninety degree phase-shifted version of the second test tone signal to the quadrature modulation branch input. The level of an undesired upper sideband frequency component in the output signal is measured and in response base band gains the in-phase and quadrature modulation branches and a local oscillator phase error are adjusted to minimize the undesired side band.

Abstract: A quadrature modulator and a method of calibrating same by applying a first test tone signal to an in-phase modulation branch input of the modulator and a ninety degree phase-shifted version of the first test tone signal to a quadrature modulation branch input of the modulator. The carrier leakage level in an output signal of the modulator is measured and in response base band dc offset voltages are adjusted to minimize the carrier leakage. A second test tone signal is applied to the in-phase modulation branch input and a ninety degree phase-shifted version of the second test tone signal to the quadrature modulation branch input. The level of an undesired upper sideband frequency component in the output signal is measured and in response base band gains the in-phase and quadrature modulation branches and a local oscillator phase error are adjusted to minimize the undesired side band.

Abstract: A quadrature modulator and a method of calibrating same by applying a first test tone signal to an in-phase modulation branch input of the modulator and a ninety degree phase-shifted version of the first test tone signal to a quadrature modulation branch input of the modulator. The carrier leakage level in an output signal of the modulator is measured and in response base band dc offset voltages are adjusted to minimize the carrier leakage. A second test tone signal is applied to the in-phase modulation branch input and a ninety degree phase-shifted version of the second test tone signal to the quadrature modulation branch input. The level of an undesired upper sideband frequency component in the output signal is measured and in response base band gains the in-phase and quadrature modulation branches and a local oscillator phase error are adjusted to minimize the undesired sideband.

Abstract: A quadrature modulator and a method of calibrating same by applying a first test tone signal to an in-phase modulation branch input of the modulator and a ninety degree phase-shifted version of the first test tone signal to a quadrature modulation branch input of the modulator. The carrier leakage level in an output signal of the modulator is measured and in response base band dc offset voltages are adjusted to minimize the carrier leakage. A second test tone signal is applied to the in-phase modulation branch input and a ninety degree phase-shifted version of the second test tone signal to the quadrature modulation branch input. The level of an undesired upper sideband frequency component in the output signal is measured and in response base band gains the in-phase and quadrature modulation branches and a local oscillator phase error are adjusted to minimize the undesired sideband.