Abstract: Disclosed techniques relate to memory space management for graphics processing. In some embodiments, first and second graphics cores are configured to execute instructions for multiple threadgroups. In some embodiments, the threads groups include a first threadgroup with multiple single-instruction multiple-data (SIMD) groups configured to execute a first shader program and a second threadgroup with multiple SIMD groups configured to execute a second, different shader program. Control circuitry may be configured to provide access to data stored in memory circuitry according to a shader memory space. The shader memory space may be accessible to threadgroups executed by the first graphics shader core, including the first and second threadgroups, but is not accessible to threadgroups executed by the second graphics shader core. Disclosed techniques may reduce latency, increase bandwidth available to the shader, reduce coherency cost, or any combination thereof.

Abstract: A ray tracing unit is implemented in a graphics rendering system. The ray tracing unit comprises: processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. Core ray data for rays to be processed by the processing logic is stored in the dedicated ray memory, and at least some non-core ray data for the rays is stored in the memory system. This allows core ray data for many rays to be stored in the dedicated ray memory without the size of the dedicated ray memory becoming too wasteful when the ray tracing unit is not in use.

Abstract: An apparatus includes a decoding circuit, and a communication bus that is configured to transfer a particular data payload and a control signal that indicates whether the particular data payload includes a mask value. The mask value is indicative of enabled and non-enabled data words in the particular data payload. The decoding circuit is configured to receive, from an encoding circuit via the communication bus, the particular data payload and the control signal. In response to a determination that the control signal indicates that the particular data payload does not include the mask value, the decoding circuit is configured to use a default value for the mask value, and to create an uncompressed data payload from the particular data payload using the default value, wherein the default value causes the decoding circuit to maintain positions of data words between the particular data payload and the uncompressed data payload.

Abstract: An apparatus for cleaning a fabric article includes an emitting header that emits fluid towards the fabric article and a suction header that suctions the fluid emitted by the emitting header. The suction header and the emitting header are parallel to each other and separated from each other by a space. The space is configured for positioning the fabric article in the space so that fluid emitted by the emitting header flows through the fabric article towards the suction header. A washing appliance for cleaning a fabric article includes a detergent compartment, a control system monitor, a pump, a water compartment, an emitting header that emits fluid towards the fabric article, a suction header that suctions the fluid emitted by the emitting header, a screen disposed between the emitting header and the suction header, and a servo motor in communication with at least one of the emitting header and the suction header.

Abstract: An apparatus for cleaning a fabric article includes an emitting header that emits fluid towards the fabric article and a suction header that suctions the fluid emitted by the emitting header. The suction header and the emitting header are parallel to each other and separated from each other by a space. The space is configured for positioning the fabric article in the space so that fluid emitted by the emitting header flows through the fabric article towards the suction header. A washing appliance for cleaning a fabric article includes a detergent compartment, a control system monitor, a pump, a water compartment, an emitting header that emits fluid towards the fabric article, a suction header that suctions the fluid emitted by the emitting header, a screen disposed between the emitting header and the suction header, and a servo motor in communication with at least one of the emitting header and the suction header.

Abstract: Disclosed techniques relate to ray intersection processing for ray tracing. In some embodiments, ray intersection circuitry traverses a spatially organized acceleration data structure and includes bounding region circuitry configured to test, in parallel, whether a ray intersects multiple different bounding regions indicated by a node of the data structure. Shader circuitry may execute a ray intersect instruction to invoke traversal by the ray intersect circuitry and the traversal may generate intersection results. The shader circuitry may shade intersected primitives based on the intersection results. Disclosed techniques that share processing between intersection circuitry and shader processors may improve performance, reduce power consumption, or both, relative to traditional techniques.

Abstract: Disclosed techniques relate to primitive testing associated with ray intersection processing for ray tracing. In some embodiments, shader circuitry executes a first SIMD group that includes a ray intersect instruction for a set of rays. Ray intersect circuitry traverses, in response to the ray intersect instruction, multiple nodes in a spatially organized acceleration data structure (ADS). In response to reaching a node of the ADS that indicates one or more primitives, the apparatus forms a second SIMD group that executes one or more instructions to determine whether a set of rays that have reached the node intersect the one or more primitives. The shader circuitry may execute the first SIMD group to shade one or more primitives that are indicated as intersected based on results of execution of the second SIMD group. Thus, disclosed techniques may use both dedicated ray intersect circuitry and dynamically formed SIMD groups executed by shader processors to detect ray intersection.

Abstract: Disclosed techniques relate to grouping rays during traversal of a spatially-organized acceleration data structure (e.g., a bounding volume hierarchy) for ray intersection processing. The grouping may provide temporal locality for accesses to bounding region data. In some embodiments, ray intersect circuitry is configured to group rays based on the node of the data structure that they target next. The ray intersect circuitry may select one or more groups of rays for issuance each clock cycle, e.g., to bounding region test circuitry.

Abstract: Disclosed techniques relate to forming single-instruction multiple-data (SIMD) groups during ray intersection traversal. In particular, ray intersection circuitry may include dedicated circuitry configured to traverse an acceleration data structure, but may dynamically form a SIMD group to transform ray coordinates when traversing from one level of the data structure to another. This may allow shader processors to execute the SIMD group to perform the transformation. Disclosed techniques may facilitate instancing of graphics models within the acceleration data structure.

Abstract: Disclosed techniques relate to an acceleration data structure for ray intersection with a many-to-many mapping between bounding regions and primitives. In some embodiments, one or more graphics processors access data for multiple graphics primitives in a graphics scene and generate a spatially organized data structure. Some nodes of the data structure indicate graphics primitives and some nodes indicate coordinates of bounding regions in the graphics scene. In some embodiments, the spatially organized data structure includes a node with a bounding region for which multiple primitives are indicated as children and also includes a primitive for which multiple bounding regions are indicated as parents. Disclosed techniques may generate bounding regions that closely fit primitives, which may reduce primitive testing for ray tracing. This in turn may increase performance or reduce power consumption relative to traditional techniques.

Abstract: An apparatus includes a decoding circuit, and a communication bus that is configured to transfer a particular data payload and a control signal that indicates whether the particular data payload includes a mask value. The mask value is indicative of enabled and non-enabled data words in the particular data payload. The decoding circuit is configured to receive, from an encoding circuit via the communication bus, the particular data payload and the control signal. In response to a determination that the control signal indicates that the particular data payload does not include the mask value, the decoding circuit is configured to use a default value for the mask value, and to create an uncompressed data payload from the particular data payload using the default value, wherein the default value causes the decoding circuit to maintain positions of data words between the particular data payload and the uncompressed data payload.

Abstract: A ray-tracing system for performing intersection testing includes a tester module for testing rays for intersection with a volume, the tester module receiving a packet of one or more rays to be tested for intersection with the volume. A first set of one or more testers performs intersection testing at a first level of precision to provide intersection testing results, wherein for a first type of the intersection testing result from the first set of one or more testers intersection testing does not need to be reperformed at a second level of precision greater than the first level of precision, and for a second type of the intersection testing result from the first set of one or more testers intersection testing is to be reperformed at the second level of precision; and a second set of one or more testers configured to perform intersection testing at the second level of precision.

Abstract: A ray-tracing system configured to perform intersection testing, comprising: a tester module for testing rays for intersection with a volume, the tester module being configured to receive a packet of one or more rays to be tested for intersection with the volume, wherein the tester module comprises: a first set of one or more testers configured to perform intersection testing at a first level of precision to provide intersection testing results, wherein for a first type of the intersection testing result from the first set of one or more testers intersection testing does not need to be reperformed at a second level of precision greater than the first level of precision, and for a second type of the intersection testing result from the first set of one or more testers intersection testing is to be reperformed at the second level of precision; and a second set of one or more testers configured to perform intersection testing at the second level of precision; wherein the tester module is configured to: allocate

Abstract: An apparatus includes an encoding circuit, and a communication bus having conductive traces configured to transfer a data payload, including a control signal and up to a maximum number of data words. The encoding circuit is configured to receive an uncompressed data payload and a mask value, and to create, using the mask value, the control signal, the control signal indicative of whether the uncompressed data payload includes one or more non-enabled data words. In response to a determination that the control signal indicates that the uncompressed data payload includes one or more non-enabled data words, the encoding circuit is configured to create a compressed data payload from the uncompressed data payload, and to send, to a decoding circuit, the compressed data payload and the control signal via the plurality of conductive traces of the communication bus. The compressed data payload includes the mask value.

Abstract: A ray tracing unit is implemented in a graphics rendering system. The ray tracing unit comprises: processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. Core ray data for rays to be processed by the processing logic is stored in the dedicated ray memory, and at least some non-core ray data for the rays is stored in the memory system. This allows core ray data for many rays to be stored in the dedicated ray memory without the size of the dedicated ray memory becoming too wasteful when the ray tracing unit is not in use.

Abstract: A ray tracing unit is implemented in a graphics rendering system. The ray tracing unit comprises: processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. Core ray data for rays to be processed by the processing logic is stored in the dedicated ray memory, and at least some non-core ray data for the rays is stored in the memory system. This allows core ray data for many rays to be stored in the dedicated ray memory without the size of the dedicated ray memory becoming too wasteful when the ray tracing unit is not in use.

Abstract: A method for preparing multi-wall carbon nanotubes comprising atomizing a precursor solution comprising an aromatic hydrocarbon and a carrier gas. The mixture is then injected through an ultrasonic atomization system to form atomized precursor droplets. Then by injecting the atomized precursor droplets from the top of a vertical chemical vapor deposition reactor, the droplets can then react with a reaction gas in the reactor vessel to form a film that adsorbs to a growth surface in the reactor vessel. Layer by layer multi-wall carbon nanotubes are formed. This method is repeated to form layers of the multi-wall carbon nanotubes. The nanotubes formed have an outer diameter of 10 nm-51 nm and a length to diameter aspect ratio of 7200-13200.

Abstract: A method for preparing multi-wall carbon nanotubes comprising atomizing a precursor solution comprising an aromatic hydrocarbon and a carrier gas. The mixture is then injected through an ultrasonic atomization system to form atomized precursor droplets. Then by injecting the atomized precursor droplets from the top of a vertical chemical vapor deposition reactor, the droplets can then react with a reaction gas in the reactor vessel to form a film that adsorbs to a growth surface in the reactor vessel. Layer by layer multi-wall carbon nanotubes are formed. This method is repeated to form layers of the multi-wall carbon nanotubes. The nanotubes formed have an outer diameter of 10 nm-51 nm and a length to diameter aspect ratio of 7200-13200.

Abstract: A method for preparing multi-wall carbon nanotubes comprising atomizing a precursor solution comprising an aromatic hydrocarbon and a carrier gas. The mixture is then injected through an ultrasonic atomization system to form atomized precursor droplets. Then by injecting the atomized precursor droplets from the top of a vertical chemical vapor deposition reactor, the droplets can then react with a reaction gas in the reactor vessel to form a film that adsorbs to a growth surface in the reactor vessel. Layer by layer multi-wall carbon nanotubes are formed. This method is repeated to form layers of the multi-wall carbon nanotubes. The nanotubes formed have an outer diameter of 10 nm-51 nm and a length to diameter aspect ratio of 7200-13200.

Abstract: A method for preparing multi-wall carbon nanotubes comprising atomizing a precursor solution comprising an aromatic hydrocarbon and a carrier gas. The mixture is then injected through an ultrasonic atomization system to form atomized precursor droplets. Then by injecting the atomized precursor droplets from the top of a vertical chemical vapor deposition reactor, the droplets can then react with a reaction gas in the reactor vessel to form a film that adsorbs to a growth surface in the reactor vessel. Layer by layer multi-wall carbon nanotubes are formed. This method is repeated to form layers of the multi-wall carbon nanotubes. The nanotubes formed have an outer diameter of 10 nm-51 nm and a length to diameter aspect ratio of 7200-13200.