Patents by Inventor Ali Razavieh

Ali Razavieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10872962
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a plurality of source/drains disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a plurality of trenches, each trench extending to a corresponding one of the plurality of source/drains. A trench contact is formed in each of the trenches in contact with the corresponding source/drain. A recess is formed in a portion of each trench contact below a top surface of the cap. A bi-stable resistive system (BRS) material is deposited in each recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch for each of the corresponding source/drains.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: December 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • Publication number: 20200373410
    Abstract: A method of fabricating a semiconductor device is provided, which includes providing a plurality of fins over a substrate and forming a plurality of first gate structures having a first gate pitch and a plurality of second gate structures having a second gate pitch traversing across a first and a second set of fins, respectively. The second gate pitch is wider than the first gate pitch. Epitaxial regions are formed between adjacent second gate structures in the second set of fins. A dielectric layer is deposited over the second gate structures and the epitaxial regions. Contact openings are formed in the dielectric layer. At least one of the contact openings is formed over the second gate structure where the second gate structure traverses across the second set of fins. The contact openings are filled with a conductive material to form contact structures electrically coupled to the second gate structures.
    Type: Application
    Filed: May 26, 2019
    Publication date: November 26, 2020
    Inventors: TUNG-HSING LEE, SIPENG GU, JIEHUI SHU, HAITING WANG, ALI RAZAVIEH, WENJUN LI, KAVYA SREE DUGGIMPUDI, TAMILMANI ETHIRAJAN, BRADLEY MORGENFELD, DAVID NOEL POWER
  • Publication number: 20200365728
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a vertical field effect transistor with optimized fin size and improved fin stability and methods of manufacture. The structure includes: a fin structure composed of substrate material, the fin structure includes: a trimmed channel region of the substrate material; a top source/drain region above the trimmed channel region and having a larger cross-section than the trimmed channel region; and a bottom source/drain region below the trimmed channel region and having a larger cross-section than the trimmed channel region; and gate material surrounding the trimmed channel region.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 19, 2020
    Inventors: Ali RAZAVIEH, Ruilong XIE
  • Patent number: 10818803
    Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A source/drain region is connected with a channel layer, and a gate structure extends across the channel layer. The channel layer is composed of a two-dimensional material.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ali Razavieh
  • Publication number: 20200144385
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.
    Type: Application
    Filed: January 3, 2020
    Publication date: May 7, 2020
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • Patent number: 10566436
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • Publication number: 20190252465
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a trench extending to the source/drain. A trench contact is formed in the trench in contact with the source/drain. A recess is formed in a portion of the trench contact below a top surface of the cap using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch.
    Type: Application
    Filed: February 12, 2018
    Publication date: August 15, 2019
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • Publication number: 20190252507
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a plurality of source/drains disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a plurality of trenches, each trench extending to a corresponding one of the plurality of source/drains. A trench contact is formed in each of the trenches in contact with the corresponding source/drain. A recess is formed in a portion of each trench contact below a top surface of the cap. A bi-stable resistive system (BRS) material is deposited in each recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch for each of the corresponding source/drains.
    Type: Application
    Filed: February 12, 2018
    Publication date: August 15, 2019
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • Publication number: 20190252508
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.
    Type: Application
    Filed: April 2, 2019
    Publication date: August 15, 2019
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • Patent number: 10256316
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • Patent number: 10236292
    Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Puneet H. Suvarna, Hiroaki Niimi, Steven J. Bentley, Ali Razavieh
  • Patent number: 10192867
    Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Puneet H. Suvarna, Hiroaki Niimi, Steven J. Bentley, Ali Razavieh
  • Patent number: 10170520
    Abstract: Fabricating a negative capacitance steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin, a source/drain, a gate, a cap disposed upon the gate, a trench contact disposed upon the source/drain, and an inter-layer dielectric. A source/drain recess is formed in the inter-layer dielectric extending to the trench contact, and a gate recess is formed in the inter-layer dielectric extending to the gate. A ferroelectric material is deposited within the gate recess, and a source/drain contact is formed within the source/drain recess. A gate contact is formed within the gate recess, and a contact recess is formed in a portion of the source/drain contact. A bi-stable resistive system (BRS) material is formed in the contact recess, and a metallization layer contact is formed upon the BRS material. A portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forms a reversible switch.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • Patent number: 9991352
    Abstract: A method that includes forming a patterned stack of materials comprising at least one channel semiconductor material layer and first and second layers of sacrificial material positioned above and below, respectively, the at least one channel semiconductor material layer, forming a replacement gate cavity above the patterned stack of materials and performing an etching process through the gate cavity to selectively remove at least a portion of the first and second layers of sacrificial material relative to the at least one channel semiconductor material layer. The method further includes performing a second etching process to form a reduced-thickness portion of the channel semiconductor material layer that has a final thickness that is less than the initial thickness and forming a replacement gate structure around at least the reduced-thickness portion of the channel semiconductor material layer.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 5, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Julien Frougier, Ali Razavieh, Ruilong Xie, Steven Bentley