Abstract: In one embodiment, the present invention includes a cache memory having a plurality of cache lines to store data, in which at least some of the cache lines are adapted to store data in a compressed state. The cache memory also may include a first tag corresponding to each of the cache lines to indicate whether data in the corresponding cache line is compressible.

Abstract: Methods and apparatus to provide unbounded transactional memory systems are described. In one embodiment, an operation corresponding to a software transactional memory (STM) access may be executed if a preceding hardware transactional memory (HTM) access operation fails.

Abstract: For a variable accessed at least once in a software-based transactional memory system (STM) defined (STM-defined) critical region of a program, modifying an access to the variable that occurs outside any STM-defined critical region system by starting a hardware based transactional memory based transaction, within the hardware based transactional memory based transaction, checking if the variable is currently owned by a STM transaction, checking if the variable is currently owned by a STM transaction; if the variable is not currently owned by a STM transaction, performing the access and then committing the hardware based transactional memory transaction; and if the variable is currently owned by a STM transaction, performing a responsive action.

Abstract: A compiler or runt-time system may determine a prefetch point to insert an instruction in order to prefetch a memory location and thereby reduce latency in accessing information from a cache. A prefetch predictor generator may decide where and whether to insert the appropriate instructions by looking at information from a hardware monitor. For example, information about cache misses may be analyzed. The differences between target addresses of those cache misses for different instructions may be determined. This information may also be used to determine the locations in the program where the prefetch instructions should be placed, as well as to calculate the address of the memory location being prefetched.

Abstract: In a multi-threaded program, a thread, of a set of threads sharing a synchronization barrier, indicating that the thread has reached the synchronization barrier to each other thread of the set of threads, the thread beginning a transactional memory based transaction after the indicating, and the thread continuing execution past the synchronization barrier after beginning the transactional memory based transaction.

Abstract: According to one embodiment of the invention, a method comprises verifying that a cache block is not exclusively owned, and if not, transmitting a message identifying both the cache block and a caching agent requesting ownership of the cache block to a broadcast interconnect.

Abstract: Provided is a method, system, and program for coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions. A hardware transaction executing in hardware transactional memory initiates a request to access a memory location. A fault is returned to the hardware transaction request in response to an operation by one software transaction executing in a software transactional memory.

Abstract: In a system comprising a transactional memory architecture, initiating a transactional memory based transaction and then, within the transaction, checking a lock and if the lock is free, executing a critical section.

Abstract: A system includes a processor and a size bounded first-in first-out (FIFO) memory that is connected to the processor and a display is connected to the processor. A managing process to run on the processor to manage the FIFO memory structure. The FIFO memory includes a counter portion and a value portion for each of a tail portion and a head portion, and the managing process is non-blocking. The counter portion is used as a timestamp to maintain FIFO order.

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a central processing unit (CPU), a cache memory coupled to the CPU and a cache controller coupled to the cache memory. The cache memory includes a plurality of compressible cache lines to store additional data. The cache controller includes compression logic to compress one or more of the plurality of cache lines into compressed cache lines, and hint logic to store hint information in unused space within the compressed cache lines.

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a central processing unit (CPU), a cache memory coupled to the CPU and a cache controller, coupled to the cache memory. The cache memory includes a plurality of compressible cache lines to store additional data. The cache controller reorders a cache line after each access to the cache line prior to the compression of the cache line into a compressed cache line.

Abstract: A computer system includes a central processing unit (CPU) and a cache memory coupled to the CPU. The cache memory includes a plurality of compressible cache lines to store additional data.

Abstract: Methods and apparatuses for dynamic type checking are described. For one embodiment runtime code generation is used to effect dynamic type checking by generating code specialized to different object types. For one embodiment a virtual dynamic type check (DTC) function is generated for each object at run time. The virtual DTC function contains a sequence of instructions to type check every element (type) within an object's type hierarchy. The virtual DTC function is tailored for a particular type and thus conducts dynamic type checking more efficiently for objects of the particular type. For one embodiment the DTC function can complete type checking of interface type hierarchies. For one embodiment a compiler may determine whether a type is a class type or interface type and may generate a virtual DTC function only for interface types.

Abstract: Techniques are described for optimizing memory management in a processor system. The techniques may be implemented on processors that include on-chip performance monitoring and on systems where an external performance monitor is coupled to a processor. Processors that include a Performance Monitoring Unit (PMU) are examples. The PMU may store data on read and write cache misses, as well as data on translation lookaside buffer (TLB) misses. The data from the PMU is used to determine if any memory regions within a memory heap are delinquent memory regions, i.e., regions exhibiting high numbers of memory problems or stalls. If delinquent memory regions are found, the memory manager, such as a garbage collection routine, can efficiently optimize memory performance as well as the mutators performance by improving the layout of objects in the heap. In this way, memory management routines may be focused based on dynamic and real-time memory performance data.

Abstract: In one embodiment, the present invention includes a cache memory having a plurality of cache lines to store data, in which at least some of the cache lines are adapted to store data in a compressed state. The cache memory also may include a first tag corresponding to each of the cache lines to indicate whether data in the corresponding cache line is compressible.

Abstract: A method, apparatus and system including determining a distance between centers of at least two consecutive histogram bins, comparing the distance with a selected threshold value, determining major execution phases of an executable process based on the comparison, and filtering each buffer of sequenced buffers to detect hot buffers.

Abstract: Thread synchronization with lock inflation methods and apparatus for managed run-time environments are disclosed. An example method disclosed herein comprises determining a locking operation to perform on a lock corresponding to the object, performing an optimistically balanced synchronization of the lock if the locking operation is not unbalanced, and modifying a lock shape of the lock if the locking operation is unbalanced.

Abstract: Thread synchronization methods and apparatus for managed run-time environments are disclosed. An example method disclosed herein comprises determining a set of locking operations to perform on a lock corresponding to an object, performing an initial locking operation comprising at least one of a balanced synchronization of the lock and an optimistically balanced synchronization of the lock if the initial locking operation is not unbalanced, and, if the initial locking operation is active and comprises the optimistically balanced synchronization, further comprising modifying a state of a pending optimistically balanced release corresponding to the optimistically balanced synchronization if a subsequent locking operation is unbalanced.

Abstract: A method and apparatus for a read barrier mechanism are described. According to an embodiment, a method comprises receiving an access request for a program object; performing a combined check for a null reference or for a read barrier for the program object; and if the combined check is affirmative, performing a recovery operation.

Abstract: A method, apparatus and system including selecting a phase threshold value, receiving a plurality of sequenced buffers, determining a distance between centers of at least two consecutive histogram bins, comparing the distance with the selected threshold value, and determining major execution phases of an executable process based on the comparison.