Patents by Inventor Ali Salman
Ali Salman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088305Abstract: A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Umamaheswari Aghoram, Akram Ali Salman, Binghua Hu, Alexei Sadovnikov
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Patent number: 11869986Abstract: A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.Type: GrantFiled: August 27, 2021Date of Patent: January 9, 2024Assignee: Texas Instruments IncorporatedInventors: Umamaheswari Aghoram, Akram Ali Salman, Binghua Hu, Alexei Sadovnikov
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Publication number: 20240005348Abstract: The disclosure features a method which includes inputting or receiving information on one or more features of a plurality of residential properties and prices of the residential properties including a marketed price, a listing price, and a closing price, providing the information to a Machine Learning Algorithm to determine the relationship between the one or more features and the prices of the residential properties to create a Machine Learned Model, inputting or receiving information on one or more features of a new residential property into the Machine Learned Model, and predicting a base price of the new residential property from the Machine Learned Model based on the one or more features of the new residential property. The disclosure also features one or more non-transitory, computer-readable storage media storing instructions capable of performing the method and a computer or computer system capable of performing the method.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Corentin Guillo, Sivakumaran Somasundaram, Pablo Lopez Santori, Ali Salman, Gordon Campbell Wells, Avnish Kumar
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Publication number: 20230210785Abstract: Invention deals with a macular carotenoid formulation comprising Carotenoids, Lutein, Zeaxanthin, Meso Zeaxanthin, Beta Carotene, Alpha Carotene, Lycopene and Cryptoxanthin in a synergistic combination. The formulation helps in increasing macular pigment optical density (MPOD) related to prevention of age-related macular degeneration (ARMD). The formulation is used as a nutrient, nutraceutical or dietary supplement. The dietary supplement may be formulated as soft gel capsules, two-piece hard-shell capsules, liquid-fill capsules, tablets, effervescent granules, gummies, powder mixes, stick packs, beverages, emulsions, bakery products, dairy products, tinctures, oil suspensions, bead-lets, powders, cold water-soluble powders, emulsions and granules or any combination thereof. The present invention can be used for the development of functional food, dietary plan and as a nutritional supplement.Type: ApplicationFiled: December 26, 2022Publication date: July 6, 2023Applicant: Biogen Extracts Pvt LtdInventor: Mohammed Ali Salman Mehkri
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Publication number: 20230066563Abstract: A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Umamaheswari Aghoram, Akram Ali Salman, Binghua Hu, Alexei Sadovnikov
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Patent number: 11521961Abstract: An integrated circuit includes a bipolar transistor, e.g. a back-ballasted NPN, that can conduct laterally and vertically. At a low voltage breakdown and low current conduction occur laterally near a substrate surface, while at a higher voltage vertical conduction occurs in a more highly-doped channel below the surface. A relatively high-resistance region at the surface has a low doping level to guide the conduction deeper into the collector.Type: GrantFiled: June 29, 2020Date of Patent: December 6, 2022Assignee: Texas Instruments IncorporatedInventors: Akram Ali Salman, Guruvayurappan Mathur, Ryo Tsukahara
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Publication number: 20220199611Abstract: In an example, an electronic device includes a first well having a first conductivity type within a semiconductor substrate and a second well having a second opposite conductivity type within the semiconductor substrate and touching the first well. The device further includes a third well having the first conductivity type within the second well. A metallic structure in direct contact with at least a portion of a surface of the third well thereby forms a Schottky barrier between the third well and the metallic structure.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Inventors: Zaichen CHEN, Akram Ali SALMAN, Henry Litzmann EDWARDS
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Publication number: 20210408270Abstract: An integrated circuit includes a semiconductor substrate having a doped region, e.g. a DWELL, with a first conductivity type. A source region is located within the doped region, the source region having a second opposite conductivity type. A drain region having the second conductivity type is spaced apart from the source region. A gate electrode is located between the source region and the drain region, the gate electrode partially overlapping the doped region. A body region having the first conductivity type is located within the doped region. A dielectric layer forms a closed path around the body region.Type: ApplicationFiled: June 24, 2021Publication date: December 30, 2021Inventors: Zaichen Chen, Akram Ali Salman
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Patent number: 10978443Abstract: A semiconductor device contains a Zener-triggered transistor having a Zener diode vertically integrated in a first current node of the Zener-triggered transistor. The first current node includes an n-type semiconductor material contacting a p-type semiconductor material in a substrate. The Zener diode includes an n-type cathode contacting the first current node, and a p-type anode contacting the n-type cathode and contacting the p-type semiconductor material. The semiconductor device may be formed using an implant mask, with an opening for the Zener diode. Boron and arsenic are implanted into the substrate in an area exposed by the opening in the implant mask. The substrate is subsequently heated to diffuse and activate the implanted boron and arsenic. The Zener-triggered transistor may be used in an ESD circuit or a snubber circuit.Type: GrantFiled: June 6, 2019Date of Patent: April 13, 2021Assignee: Texas Instruments IncorporatedInventors: Akram Ali Salman, Jun Cai, Krishna Praveen Mysore Rajagopal
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Publication number: 20210005599Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.Type: ApplicationFiled: September 22, 2020Publication date: January 7, 2021Inventors: Henry Litzmann Edwards, Akram Ali Salman
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Publication number: 20200388606Abstract: A semiconductor device contains a Zener-triggered transistor having a Zener diode vertically integrated in a first current node of the Zener-triggered transistor. The first current node includes an n-type semiconductor material contacting a p-type semiconductor material in a substrate. The Zener diode includes an n-type cathode contacting the first current node, and a p-type anode contacting the n-type cathode and contacting the p-type semiconductor material. The semiconductor device may be formed using an implant mask, with an opening for the Zener diode. Boron and arsenic are implanted into the substrate in an area exposed by the opening in the implant mask. The substrate is subsequently heated to diffuse and activate the implanted boron and arsenic. The Zener-triggered transistor may be used in an ESD circuit or a snubber circuit.Type: ApplicationFiled: June 6, 2019Publication date: December 10, 2020Applicant: Texas Instruments IncorporatedInventors: Akram Ali Salman, Jun Cai, Krishna Praveen Mysore Rajagopal
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Publication number: 20200328204Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.Type: ApplicationFiled: June 29, 2020Publication date: October 15, 2020Inventors: Akram Ali Salman, Guruvayurappan Mathur, Ryo Tsukahara
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Patent number: 10784251Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.Type: GrantFiled: April 1, 2019Date of Patent: September 22, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry Litzmann Edwards, Akram Ali Salman
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Patent number: 10700055Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.Type: GrantFiled: December 12, 2017Date of Patent: June 30, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Akram Ali Salman, Guruvayurappan Mathur, Ryo Tsukahara
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Publication number: 20200203333Abstract: An integrated circuit (IC) includes a semiconductor substrate having a first conductivity type and a transistor formed within the substrate that includes a buried layer having a second conductivity type. A first doped region, located between the buried layer and a surface of the substrate, has the first conductivity type and a second doped region, extending from the substrate surface to the buried layer, has the second conductivity type. A third doped region, located between the buried layer and the surface and between the first doped region and the second doped region, has the second conductivity type and a first dopant concentration. A fourth doped region, located between the third doped region and the substrate surface and between the first doped region and the second doped region, has a second dopant concentration less than the first dopant concentration. A method of fabricating the IC is also shown.Type: ApplicationFiled: December 21, 2018Publication date: June 25, 2020Inventors: Zaichen Chen, Akram Ali Salman
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Publication number: 20190229111Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.Type: ApplicationFiled: April 1, 2019Publication date: July 25, 2019Inventors: Henry Litzmann Edwards, Akram Ali Salman
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Publication number: 20190181134Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Applicant: Texas Instruments IncorporatedInventors: Akram Ali Salman, Guruvayurappan Mathur, Ryo Tsukahara
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Patent number: 10249607Abstract: An integrated circuit includes a stacked NPN having an upper NPN connected to a lower NPN. The upper NPN includes an upper collector, an upper base, and an upper emitter. The lower NPN includes a lower collector, a lower base, and a lower emitter. The upper collector includes collector segments on opposite sides of the lower emitter. The collector segments are laterally separated by collector separators which are aligned to orientation directions in the collector segments. The upper collector does not have collector separators across the orientation directions.Type: GrantFiled: December 15, 2017Date of Patent: April 2, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry Litzmann Edwards, Akram Ali Salman
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Patent number: 9714073Abstract: An underwater propulsion belt that propels a user underwater and includes a plurality of gates, each gate has a channel. A pump is found in each gate and is controlled independently form the other gates. A power supply powers the pumps to pump water in either direction through the channel. The underwater propulsion belt further includes circuitry configured to receive diver information from the user and from one or more sensors. The underwater propulsion belt controls, based on the information, the movement of the user. The user's position is calculated based on whether the user is in an upright or prone position, and maintains, based on the calculation, the user's balance.Type: GrantFiled: October 26, 2015Date of Patent: July 25, 2017Inventor: Ali Salman Alshafai
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Publication number: 20170113766Abstract: An underwater propulsion belt that propels a user underwater and includes a plurality of gates, each gate has a channel. A pump is found in each gate and is controlled independently form the other gates. A power supply powers the pumps to pump water in either direction through the channel. The underwater propulsion belt further includes circuitry configured to receive diver information from the user and from one or more sensors. The underwater propulsion belt controls, based on the information, the movement of the user. The user's position is calculated based on whether the user is in an upright or prone position, and maintains, based on the calculation, the user's balance.Type: ApplicationFiled: October 26, 2015Publication date: April 27, 2017Inventor: Ali Salman ALSHAFAI