Patents by Inventor Ali Sheikh
Ali Sheikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11003453Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.Type: GrantFiled: December 17, 2019Date of Patent: May 11, 2021Assignee: International Business Machines CorporationInventors: Carlos Cavanna, Reid Copeland, Chad McIntyre, Ali Sheikh
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Publication number: 20200125366Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.Type: ApplicationFiled: December 17, 2019Publication date: April 23, 2020Applicant: International Business Machines CorporationInventors: Carlos CAVANNA, Reid COPELAND, Chad MC INTYRE, Ali SHEIKH
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Patent number: 10534612Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.Type: GrantFiled: March 28, 2017Date of Patent: January 14, 2020Assignee: International Business Machines CorporationInventors: Carlos Cavanna, Reid Copeland, Chad McIntyre, Ali Sheikh
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Publication number: 20170262288Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.Type: ApplicationFiled: March 28, 2017Publication date: September 14, 2017Inventors: Carlos CAVANNA, Reid COPELAND, Chad MC INTYRE, Ali SHEIKH
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Patent number: 9626186Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.Type: GrantFiled: March 8, 2016Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventors: Carlos Cavanna, Reid Copeland, Chad McIntyre, Ali Sheikh
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Publication number: 20160188338Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.Type: ApplicationFiled: March 8, 2016Publication date: June 30, 2016Inventors: Carlos CAVANNA, Reid COPELAND, Chad MC INTYRE, Ali SHEIKH
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Patent number: 9317292Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.Type: GrantFiled: October 31, 2013Date of Patent: April 19, 2016Assignee: International Business Machines CorporationInventors: Carlos Cavanna, Reid Copeland, Chad McIntyre, Ali Sheikh
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Patent number: 9235420Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a branch instruction of the program. When an indirect branch instruction of the program is encountered a processor analyzes one of the entries in the branch target buffer to determine if the instruction address of the one entry is associated with a target address of the indirect branch instruction. If the instruction address of the one entry is associated with the target address of the indirect branch instruction a branch to the target address of the one entry is performed.Type: GrantFiled: October 31, 2013Date of Patent: January 12, 2016Assignee: International Business Machines CorporationInventors: Carlos Cavanna, Reid Copeland, Chad Mc Intyre, Ali Sheikh
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Patent number: 8725984Abstract: In computing environments that use virtual addresses (or other indirectly usable addresses) to access memory, the virtual addresses are translated to absolute addresses (or other directly usable addresses) prior to accessing memory. To facilitate memory access, however, address translation is omitted in certain circumstances, including when the data to be accessed is within the same unit of memory as the instruction accessing the data. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data. Further, in some circumstances, access checking for the data is also omitted.Type: GrantFiled: September 6, 2012Date of Patent: May 13, 2014Assignee: International Business Machines CorporationInventors: Viktor S. Gyuris, Ali Sheikh, Kirk A. Stewart
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Publication number: 20140059331Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a branch instruction of the program. When an indirect branch instruction of the program is encountered a processor analyzes one of the entries in the branch target buffer to determine if the instruction address of the one entry is associated with a target address of the indirect branch instruction. If the instruction address of the one entry is associated with the target address of the indirect branch instruction a branch to the target address of the one entry is performed.Type: ApplicationFiled: October 31, 2013Publication date: February 27, 2014Applicant: International Business Machines CorporationInventors: Carlos CAVANNA, Reid COPELAND, Chad MC INTYRE, Ali SHEIKH
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Publication number: 20140059332Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.Type: ApplicationFiled: October 31, 2013Publication date: February 27, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Carlos CAVANNA, Reid COPELAND, Chad MC INTYRE, Ali SHEIKH
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Patent number: 8639492Abstract: The illustrative embodiments provide a computer implemented method, apparatus, and computer program product for accelerating execution of a program, written in an object oriented programming language, in an emulated environment. In response to receiving a request for an accelerated communications session from a guest virtual machine in the emulated environment, a native virtual machine is initiated external to the emulated environment but within the computing device hosting the emulated environment. Thereafter, an accelerated communications link is established between the guest virtual machine and the native virtual machine. The accelerated communications link enables a transfer of managed code between the guest virtual machine and the native virtual machine. The managed code is then executed by the native virtual machine.Type: GrantFiled: August 26, 2010Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Francis Bogsanyl, Graeme Johnson, Andrew Low, Marcel Mitran, Ali Sheikh
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Patent number: 8612731Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a branch instruction of the program. When an indirect branch instruction of the program is encountered a processor analyzes one of the entries in the branch target buffer to determine if the instruction address of the one entry is associated with a target address of the indirect branch instruction. If the instruction address of the one entry is associated with the target address of the indirect branch instruction a branch to the target address of the one entry is performed.Type: GrantFiled: November 6, 2009Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Carlos Cavanna, Reid Copeland, Chad McIntyre, Ali Sheikh
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Patent number: 8364461Abstract: Native code corresponding to an invalidated trace is re-used in a system emulator. A first trace is identified. A dropped second trace is identified. The dropped second trace is associated with a first native code for emulating the second trace. If the identified first trace corresponds to the dropped second trace, the first native code is associated to the first trace, and the first native code is executed. If the identified first trace does not correspond to the dropped second trace, a second native code for emulating the first trace is created, the second native code is associated with the first trace, and the second native code is executed.Type: GrantFiled: November 9, 2009Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Theodore J Bohizic, Reid T Copeland, Ali Sheikh, Kirk A Stewart
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Publication number: 20120331262Abstract: In computing environments that use virtual addresses (or other indirectly usable addresses) to access memory, the virtual addresses are translated to absolute addresses (or other directly usable addresses) prior to accessing memory. To facilitate memory access, however, address translation is omitted in certain circumstances, including when the data to be accessed is within the same unit of memory as the instruction accessing the data. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data. Further, in some circumstances, access checking for the data is also omitted.Type: ApplicationFiled: September 6, 2012Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Viktor S. Gyuris, Ali Sheikh, Kirk A. Stewart
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Patent number: 8285968Abstract: In computing environments that use virtual addresses (or other indirectly usable addresses) to access memory, the virtual addresses are translated to absolute addresses (or other directly usable addresses) prior to accessing memory. To facilitate memory access, however, address translation is omitted in certain circumstances, including when the data to be accessed is within the same unit of memory as the instruction accessing the data. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data. Further, in some circumstances, access checking for the data is also omitted.Type: GrantFiled: September 29, 2009Date of Patent: October 9, 2012Assignee: International Business Machines CorporationInventors: Viktor S. Gyuris, Ali Sheikh, Kirk A. Stewart
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Publication number: 20110112820Abstract: Native code corresponding to an invalidated trace is re-used in a system emulator. A first trace is identified. A dropped second trace is identified. The dropped second trace is associated with a first native code for emulating the second trace. If the identified first trace corresponds to the dropped second trace, the first native code is associated to the first trace, and the first native code is executed. If the identified first trace does not correspond to the dropped second trace, a second native code for emulating the first trace is created, the second native code is associated with the first trace, and the second native code is executed.Type: ApplicationFiled: November 9, 2009Publication date: May 12, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodore J Bohizic, Reid Copeland, Ali Sheikh, Kirk A. Stewart
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Publication number: 20110113223Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a branch instruction of the program. When an indirect branch instruction of the program is encountered a processor analyzes one of the entries in the branch target buffer to determine if the instruction address of the one entry is associated with a target address of the indirect branch instruction. If the instruction address of the one entry is associated with the target address of the indirect branch instruction a branch to the target address of the one entry is performed.Type: ApplicationFiled: November 6, 2009Publication date: May 12, 2011Applicant: International Business Machines CorporationInventors: Carlos CAVANNA, Reid COPELAND, Chad MC INTYRE, Ali SHEIKH
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Publication number: 20110078388Abstract: In computing environments that use virtual addresses (or other indirectly usable addresses) to access memory, the virtual addresses are translated to absolute addresses (or other directly usable addresses) prior to accessing memory. To facilitate memory access, however, address translation is omitted in certain circumstances, including when the data to be accessed is within the same unit of memory as the instruction accessing the data. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data. Further, in some circumstances, access checking for the data is also omitted.Type: ApplicationFiled: September 29, 2009Publication date: March 31, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Viktor S. Gyuris, Ali Sheikh, Kirk A. Stewart
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Publication number: 20110054879Abstract: The illustrative embodiments provide a computer implemented method, apparatus, and computer program product for accelerating execution of a program, written in an object oriented programming language, in an emulated environment. In response to receiving a request for an accelerated communications session from a guest virtual machine in the emulated environment, a native virtual machine is initiated external to the emulated environment but within the computing device hosting the emulated environment. Thereafter, an accelerated communications link is established between the guest virtual machine and the native virtual machine. The accelerated communications link enables a transfer of managed code between the guest virtual machine and the native virtual machine. The managed code is then executed by the native virtual machine.Type: ApplicationFiled: August 26, 2010Publication date: March 3, 2011Applicant: IBM CorporationInventors: Francis Bogsanyl, Graeme Johnson, Andrew Low, Marcel Mitran, Ali Sheikh