Abstract: Embodiments disclosed herein provide systems and methods for testing and repairing various aspects of an electronic display. The electronic display includes a reference array and an active array. The electronic display also includes test circuitry used to test individual or any combination of pixels of the electronic display. Switches may be disposed between the pixels and the test circuitry to be to repair the various components of the electronic display.

Abstract: In one embodiment of the present invention, at least at one stage of a Sigma-Delta analog-to-digital converter (ADC) is disclosed to include means for receiving a voltage at least one of the inputs of an operational amplifier, the operational amplifier having at least one output coupled to the at least one of the inputs via an at least one integration capacitor, means for transforming the voltage to a current and means for integrating the current on the at least one of the integration capacitors, during integration time and varying the resistance of at least one of a variable resistors coupled to the operational amplifier during integration time.

Abstract: A digital-to-analog converter (DAC) configured to operate in high frequency and/or high resolution environments. The DAC has a segmented architecture comprising one or more least significant bit (LSB) thermometer sub-converters and one or more most significant bit (MSB) thermometer sub-converters. A binary converter can also be added. The LSB and MSB thermometer sub-converters include cell pairs with a main cell and a dummy cell. The main cell switches according to actual data, drawing power from a voltage source at each transition. To maintain a consistent voltage level at the output, the dummy cell creates a transition to draw power from the voltage source responsive to a lack of transition in the main cell. Each cell pair has a dedicated voltage source. Also, the MSB thermometer sub-converter can include a load matching circuit to match the parasitic capacitance of the LSB thermometer sub-converter at an output.

Abstract: Sharing one or more load inductors comprises receiving a first input signal at a first terminal of a first amplifier and amplifying the first input signal using the first amplifier. The first amplifier is coupled to one or more load inductors at a second terminal of the first amplifier and is coupled to one or more dedicated source inductors at a third terminal of the first amplifier. Also, a second input signal is received at a first terminal of a second amplifier amplifying the second input signal using the second amplifier. The second amplifier is coupled to the one or more load inductors at a second terminal of the second amplifier and is coupled to one or more dedicated source inductors at a third terminal of the second amplifier.

Abstract: Sharing one or more load inductors comprises receiving a first input signal at a first terminal of a first amplifier and amplifying the first input signal using the first amplifier. The first amplifier is coupled to one or more load inductors at a second terminal of the first amplifier and is coupled to one or more dedicated source inductors at a third terminal of the first amplifier. Also, a second input signal is received at a first terminal of a second amplifier amplifying the second input signal using the second amplifier. The second amplifier is coupled to the one or more load inductors at a second terminal of the second amplifier and is coupled to one or more dedicated source inductors at a third terminal of the second amplifier.

Abstract: At least some of the arithmetic operations of a filter or other digital process can be performed time sequentially, which may allow the arithmetic elements for the filter or other digital process to be used multiple times for multiple operations.

Abstract: A system and method are disclosed for providing amplification to an input signal. The amplifier comprises an amplification stage configured to provide a gain to an input signal and to produce an amplified output, wherein the amplification stage includes an interface configured to receive a biasing voltage. The amplifier also comprises a peak detection feedback network coupled to the amplification stage configured to adjust the biasing voltage, whereby the peak detection feedback network controls the gain of the amplifier.

Abstract: A system and method are disclosed for providing noise reduction in a sigma delta modulator. Reducing the noise comprises inputting a signal to a plurality of modulator stages; feeding back the signal within at least one of the modulator stages through a feedback loop having a gain wherein the feedback loop provides noise shaping.