Abstract: A method of operation of a video coding system includes: receiving a video bitstream; extracting a video syntax from the video bitstream; extracting a hypothetical reference decoder (HRD) fixed syntax from the video syntax; extracting a HRD variable syntax from the video syntax; extracting a temporal layer from the video bitstream based on the HRD fixed syntax and the HRD variable syntax; and forming a video stream based on the temporal layer for displaying on a device.

Abstract: A method of operation of a video coding system includes: receiving a video bitstream as a serial bitstream; extracting a video syntax from the video bitstream; extracting a low delay flag, a network abstraction layer (NAL) hypothetical reference decode (HRD) parameters present flag, and a video coding layer (VCL) HRD parameters present flag from the video syntax extracting a HRD syntax from the video bitstream based on the low delay flag, the NAL HRD parameters present flag, and the VCL HRD parameters present flag; extracting a temporal layer from the video bitstream based on the video syntax having the HRD syntax; and forming a video stream based on the temporal layer for displaying on a device.

Abstract: An embedded codec (EBC) circuitry includes encoder circuitry to determine a count of bits required to encode a plurality of quantized prediction residual levels in each sub-block of a plurality of sub-blocks of an image block, for a first coding scheme and a second coding scheme. The encoder circuitry allocates a bit value to a signaling bit for each sub-block of the plurality of sub-blocks, based on the determined count of bits. A value of the signaling bit represents either the first coding scheme or the second coding scheme. The encoder circuitry generates a bit-stream of the image block by selective application of either the first coding scheme or the second coding scheme on each sub-block of the plurality of sub-blocks, based on the value allocated to the signaling bit for each sub-block of the plurality of sub-blocks.

Abstract: A method and system to refine coding of P-phase data, includes receipt of an input P-phase data block. The P-phase data block may comprise a plurality of entropy coded bits and a plurality of un-coded bits of P-phase data values. A refinement step size is determined for the received input P-phase data block, based on a count of refinement bits available for coding of the plurality of un-coded bits and a block size of the input P-phase data block. A refinement start position is also determined for the received input P-phase data block. The plurality of un-coded bits of the P-phase data values are refined by allocation of the refinement bits in one or more bit-planes of the input P-phase data block, based on the determined refinement step size and the determined refinement start position.

Abstract: The buffer management methods simplify the complexity of STD buffer management for HEVC and make is easy to implement HEVC in deployed AVC/MPEG-2 networks (as legacy re-multiplexers are able to be used for re-purposing HEVC content). The buffers for base and enhancement layers are also also be managed independently before re-assembly and this simplifies the STD model. Re-assembly is still implemented before decoding an enhanced HEVC video stream.

Abstract: A technique to parameterize the quantization scheme of the attribute coding of point cloud compression algorithms is described herein. Based on fixed-point arithmetic, the algorithm calculates the quantization step size (QS) in fixed-point notation, given a user-input quantization parameter (QP).

Abstract: An embedded codec (EBC) circuitry includes encoder circuitry to determine a refinement start position in a bit-plane of an encoded data block based on a random number. The refinement start position is a position in the bit-plane based on a value of the random number. The encoder circuitry determines a refinement order in the bit-plane for refining un-coded bits present in the bit-plane, based on the determined refinement start position and a refinement step size. The refinement order is a sequence of positions of the un-coded bits in the bit-plane that will be refined in that sequence. The encoder circuitry refines the un-coded bits by allocating a refinement bit at the refinement start position in the bit-plane and then followed by the allocation of subsequent refinement bits in the determined refinement order.

Abstract: A hybrid palette-DPCM coding implementation generates a palette for the most dominant colors in an image block and an index block based on the palette. Additionally, for pixels that are not in the palette, DPCM coding is utilized. By combining palette coding and DPCM coding, the image encoding process is optimized.

Abstract: An embedded codec (EBC) circuitry includes a memory to store a plurality of one dimensional (1D) sub-blocks of quantized-transformed residual levels for a 1D image block and encoder circuitry to determine a sub-block category from a set of sub-block categories for each 1D sub-block of the plurality of 1D sub-blocks. The encoder circuitry encodes the plurality of 1D sub-blocks by application of an entropy coding scheme to generate a plurality of encoded 1D sub-blocks. The encoder circuitry allocates a plurality of refinement bits at bit-positions in bit-planes corresponding to encoded quantized-transformed residual levels in an encoded 1D sub-block of the plurality of encoded 1D sub-blocks, based on the determined sub-block category of a corresponding 1D sub-block.

Abstract: A Flexible Band Offset (FBO) apparatus and method of performing Sample Adaptive Offset (SAO) filtering within encoders and decoders, such as according to the High Efficiency Video Coding (HEVC) standard, and similarly configured coding devices. The number of Band Offset (BO) modes and the number of necessary offsets is reduced. The invention beneficially provides simpler coding, reduces temporary buffer size requirements, and can yield a small performance gain over existing SAO techniques of HEVC test model HM 5.

Abstract: An encoder/decoder is described using enhanced signaling mechanisms SAO parameters. The various parameters are signaled in various ways according to different embodiments of the invention. In a first embodiment (embodiment A), SAO on/off is decoupled form SAO type coding, with SAO on/off flags being jointly encoded for all color components. The second embodiment (embodiment B), is similar to embodiment A, but modified for application to JCTVC-J0268. In a third embodiment separate signaling is provided for SAO on/off, SAO types BO and EO, and for BO and EO side information (classes or band position). Each of these enhanced SAO signaling mechanisms provide enhanced coding efficiency.

Abstract: An embedded codec (EBC) circuitry includes encoder circuitry to encode a plurality of sub-blocks of an image block by an entropy coding scheme to generate a plurality of encoded data blocks. Each encoded data block includes a first plurality of bit-planes and a second plurality of bit-planes. The first plurality of bit-planes include a plurality of entropy coded bits. The encoder circuitry determines a count of refinement bits of a plurality of refinement bits, for an encoded data block of the plurality of encoded data blocks, based on a quality measure of the plurality of encoded data blocks. The quality measure represents a count of the plurality of entropy coded bits in each encoded data block. The encoder circuitry allocates the count of refinement bits in the second plurality of bit-planes of the encoded data block.

Abstract: An image-processing apparatus and method for quantization partitioning for enhanced image compression, includes storage of an input image in a first storage space having a first storage access bandwidth. The image-processing apparatus selects a plurality of QP values from a defined QP range for a first block of a plurality of blocks of the input image. The plurality of QP values are selected from the defined QP range based on defined criteria. The image-processing apparatus is configured to encode, by the selected plurality of QP values, the first block to generate an encoded bit stream of the first block. The encoded bit stream of the first block is storable in a reduced second storage space in the memory with a reduced second storage access bandwidth.

Abstract: Embedded codec (EBC) circuitry includes a memory to store a plurality of blocks of quantized-transformed residual levels for a plurality of image blocks of an input image and encoder circuitry to classify a plurality of quantized-transformed residual levels in a first block of the plurality of blocks, into a first set of quantized-transformed residual levels and a second set of quantized-transformed residual levels. The encoder circuitry applies a first entropy coding scheme on the first set of quantized-transformed residual levels, and a combination of the first entropy coding scheme and a second entropy coding scheme on the second set of quantized-transformed residual levels in a Direct Current-to-Alternating Current (DC-to-AC) scan order in the first block. A bit-stream of encoded image block is generated, by the encoder circuitry, by application of the first entropy coding scheme and the combination of the first entropy coding scheme and the second entropy coding scheme.

Abstract: Embedded Codec (EBC) circuitry for image block coding based on pixel-domain pre-processing operations on image block is provided. The EBC circuitry includes memory that stores a first image block and encoder circuitry that computes a first sum of absolute differences (SAD) from a first prediction block of row-wise residual values and a second SAD from a second prediction block of column-wise residual values in pixel-domain. The encoder circuitry selects a residual prediction type from a set of residual prediction types as an optimal residual prediction type and a set of quantization parameters as optimal quantization parameters for each of a first encoding mode and a second encoding mode. The encoder circuitry generates a set of bit-streams of encoded first image block in the first encoding mode and the second encoding mode, respectively, based on the selected residual prediction type and the selected set of quantization parameters.

Abstract: An embedded codec (EBC) circuitry includes a memory to store a plurality of one dimensional (1D) sub-blocks of quantized-transformed residual levels for a 1D image block and encoder circuitry to allocate a set of signaling bits to each 1D sub-block of the plurality of 1D sub-blocks. The encoder circuitry selects an entropy coding scheme, from a set of entropy coding schemes, for each 1D sub-block of the plurality of 1D sub-blocks, based on the allocated set of signaling bits for each 1D sub-block. The encoder circuitry generates a bit-stream of encoded 1D image block by selective application of the entropy coding scheme on a DC quantized-transformed residual level, a plurality of AC quantized-transformed residual levels, or a combination of the DC quantized-transformed residual level and the plurality of AC quantized-transformed residual levels of each 1D sub-block of the plurality of 1D sub-blocks.

Abstract: A point cloud compression approach that exploits HEVC for compression of both the geometry and color data is described herein. Although both the geometry and color could be compressed in a lossy fashion, the point cloud compression approach is suggested for the scenario of lossless geometry and lossy color coding. Both geometry and color data are first mapped into 2D images and then compressed by HEVC. A sorting technique is used to sort the geometry data to make it as correlated as possible when it is mapped to a 2D image. For color coding, clustering is used to put similar colors in a point cloud into spatial neighbors in the mapped 2D image. This significantly avoids color leaking due to quantization errors to neighbor points in 3D. The results show that much better compression is achieved compared to the Anchor when it is configured for lossless geometry coding.

Abstract: Embedded codec (EBC) circuitry includes a memory to store a plurality of blocks of quantized-transformed residual levels for a plurality of image blocks of an input image and encoder circuitry to classify a plurality of quantized-transformed residual levels in a first block of the plurality of blocks, into a first set of quantized-transformed residual levels and a second set of quantized-transformed residual levels. The encoder circuitry applies a first entropy coding scheme on the first set of quantized-transformed residual levels, and a combination of the first entropy coding scheme and a second entropy coding scheme on the second set of quantized-transformed residual levels in a Direct Current-to-Alternating Current (DC-to-AC) scan order in the first block. A bit-stream of encoded image block is generated, by the encoder circuitry, by application of the first entropy coding scheme and the combination of the first entropy coding scheme and the second entropy coding scheme.

Abstract: An embedded decoder circuitry for bias minimization in successively reconstructed images from a decoded image obtained from an encoded input image, includes an on-chip memory and a bias control circuit communicatively coupled to the on-chip memory. The on-chip memory stores transform-domain compressed data that includes a plurality of transform blocks of an input image. The bias control circuit is configured to determine a set of conditions associated with each transform coefficient in a transform block of the encoded input image and modify a set of transform coefficients from the plurality of transform coefficients in the transform block based on determination of the set of conditions. The bias control circuit is further configured to generate a decoded image that exhibits a reduced error propagation in successively reconstructed images with respect to the input image, based on inverse transformation of each transform block of the encoded input image.

Abstract: A Flexible Band Offset (FBO) apparatus and method of performing Sample Adaptive Offset (SAO) filtering within encoders and decoders, such as according to the High Efficiency Video Coding (HEVC) standard, and similarly configured coding devices. The number of Band Offset (BO) modes and the number of necessary offsets is reduced. The invention beneficially provides simpler coding, reduces temporary buffer size requirements, and can yield a small performance gain over existing SAO techniques of HEVC test model HM 5.