Patents by Inventor Ali Y. Duale
Ali Y. Duale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140250330Abstract: Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution, testing, by the computing device, the transaction execution in a uni-processing system based on the instruction stream, and outputting, by the computing device, a status of the test to one or more output devices. A determination may be made that an abort occurs in the transaction execution based on the testing.Type: ApplicationFiled: March 1, 2013Publication date: September 4, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ali Y. Duale, Shailesh R. Gami, Dennis W. Wittig
-
Publication number: 20140250329Abstract: Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output to one or more output devices.Type: ApplicationFiled: March 1, 2013Publication date: September 4, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ali Y. Duale, Dennis W. Wittig
-
Publication number: 20140245074Abstract: A computer program product is provided for performing a method including: generating a test instruction stream of a program that includes a plurality of executable instructions; setting controls for a runtime-instrumentation process; simulating execution of the test instruction stream and sampling of the test instruction stream according to the controls, and storing simulated records associated with the sampling in a predicted collection buffer (PCB); accessing a program buffer of a processor, the program buffer storing records associated with sampling the test instruction stream according to the controls during execution of the test instruction stream by the processor; examining individual records in the program buffer to determine whether the individual records are valid and in proper sequence; and comparing the simulated records of the PCB and the records of the program buffer to validate the program buffer.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ali Y. Duale, Shailesh R. Gami, Sandhya Venugopala, Dennis Wittig
-
Publication number: 20140081615Abstract: According to exemplary embodiments, a computer program product for testing virtual systems includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method comprises randomly selecting commands from a pool of commands, generating by a computer a test sequence from the randomly selected commands and simulating performance of the test sequence for a simulated virtual system that is a model of a virtual system. The method also includes recording simulated results of the simulated performance, performing the test sequence on the virtual system, recording actual results of the test sequence being performed on the virtual system, and determining by a computer if the virtual system is operating properly based on a comparison of the simulated results to the actual results.Type: ApplicationFiled: November 22, 2013Publication date: March 20, 2014Applicant: INTERNATIONAL BUSINESS MACHINES COPORATIONInventors: Mohammed Abdirashid, Michael E. Browne, Ali Y. Duale
-
Publication number: 20130191105Abstract: According to exemplary embodiments, a computer program product for testing virtual systems includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method comprises randomly selecting commands from a pool of commands, generating by a computer a test sequence from the randomly selected commands and simulating performance of the test sequence for a simulated virtual system that is a model of a virtual system. The method also includes recording simulated results of the simulated performance, performing the test sequence on the virtual system, recording actual results of the test sequence being performed on the virtual system, and determining by a computer if the virtual system is operating properly based on a comparison of the simulated results to the actual results.Type: ApplicationFiled: January 20, 2012Publication date: July 25, 2013Applicant: INTERNATIONAL BUSINESS MACHINES COPORATIONInventors: Mohammad Abdirashid, Michael E. Browne, Ali Y. Duale
-
Patent number: 8479172Abstract: A system for testing a base machine includes the base machine that has a base feature set (BFS) and a testing module. The system also includes a test case generator, configured to: select a prior level of the base machine, the prior level having a legacy architecture; determine a feature set of the legacy architecture based on the BFS; generate a set of test instructions based on the feature set; and provide the set of test instructions to the testing module.Type: GrantFiled: November 23, 2010Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Ali Y. Duale, Shailesh R. Gami, Dennis W. Wittig
-
Publication number: 20120131560Abstract: A system for testing a base machine includes the base machine that has a base feature set (BFS) and a testing module. The system also includes a test case generator, configured to: select a prior level of the base machine, the prior level having a legacy architecture; determine a feature set of the legacy architecture based on the BFS; generate a set of test instructions based on the feature set; and provide the set of test instructions to the testing module.Type: ApplicationFiled: November 23, 2010Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ali Y. Duale, Shailesh R. Gami, Dennis W. Wittig
-
Patent number: 8037116Abstract: A method of streamlining floating-point conversions includes determining a source coefficient and a source exponent of an input value represented by a floating-point number in a source base; estimating an approximated target exponent (ATE) using the source coefficient and the source exponent, in the event the source coefficient has a non-zero value; determining whether the ATE exceeds a maximum exponent so as to result an overflow, and outputting a predefined overflow value in the event of an overflow; determining whether the ATE exceeds a minimum exponent so as to result an underflow, and outputting a predefined underflow value in the event of an underflow; and in the event the ATE does not result in either an overflow or underflow, converting the input value to an output value represented by a converted coefficient, a converted base and the exponent of the output value.Type: GrantFiled: May 21, 2007Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Trevor E. Carlson, Ali Y. Duale
-
Patent number: 7991811Abstract: A method of performing floating-point conversions in a digital computing system includes determining a source coefficient, c1, and a source exponent, n, of an input value represented by a floating-point number in a source base, b1; converting the source coefficient to a common base, b2, and storing the converted coefficient in a first digit collection; iteratively multiplying the contents of the first digit collection by b1 and storing the intermediate results therein, wherein one or more overflow bits of the first digit collection are carried and added to one or more additional digit collections once a nonzero value is reached; and an output value in the common base is stored in the digit collections after n multiplication iterations, represented by c2×b2m, wherein c2 is the converted coefficient of the output value in the common base b2 and m is the exponent of the output value.Type: GrantFiled: April 17, 2007Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Erik T. Carlson, Ali Y. Duale
-
Publication number: 20110145308Abstract: A system to improve numerical conversion may include a data processor and a controller configured to convert a floating-point number from the data processor to more than one different floating-point type number. The conversion may enable the selection of the more than one different floating-point type number that satisfies the requirements of an executing application and/or is closest to the original number.Type: ApplicationFiled: December 15, 2009Publication date: June 16, 2011Applicant: INTERNATIONA BUSINESS MACHINES CORPORATIONInventor: Ali Y. Duale
-
Patent number: 7917326Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.Type: GrantFiled: January 30, 2008Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventors: Theodore J. Bohizic, Ali Y. Duale, Dennis W. Wittig
-
Patent number: 7904270Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.Type: GrantFiled: January 30, 2008Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Theodore J. Bohizic, Ali Y. Duale, Dennis W. Wittig
-
Patent number: 7877742Abstract: A method, system, and computer program product for generating terminating, pseudo-random test instruction streams, including forward and backward branching instructions. A first instruction stream is generated, including at least one backward branching instruction and at least one forward branching instruction. Each backward branching instruction is preceded by at least one forward branching instruction, which is used to guarantee termination of the loop formed by the backward branching instruction. Backward branching targets are resolved when the backward branching instruction is inserted into the first instruction stream. Forward branching targets remain unresolved in the first instruction stream. A set of potential branch targets is determined for each forward branching instruction. For each forward branching instruction, a branch target is randomly selected from the set of potential branch targets for that forward branching instruction.Type: GrantFiled: June 8, 2006Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Ali Y. Duale, Theodore J. Bohizic, Dennis W. Wittig
-
Patent number: 7827451Abstract: A method, system and program product are provided for establishing one or more decimal floating point (DFP) operand for facilitating testing of a decimal floating point instruction. The method includes obtaining an encoded DFP operand previously generated for testing the decimal floating point instruction, and logically modifying at least one bit of the encoded DFP operand without decoding the encoded DFP operand to obtain an additional encoded DFP operand. In one embodiment, m sequential bits of the encoded DFP operand, n randomly generated bits (wherein n=m), and a logical operation (such as an AND, OR, XOR or SHIFT) are employed in modifying the previously generated, encoded DFP operand.Type: GrantFiled: May 24, 2006Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Theodore J. Bohizic, Mark H. Decker, Ali Y. Duale
-
Patent number: 7774668Abstract: A method for monitoring a test case generator system by detecting non-reproducible pseudo-random test cases, comprising: building a first pseudo-random test case having a first sequence of seeds comprising a first starting seed and a first ending seed through the test case generator system; reproducing the first sequence of seeds of the first pseudo-random test case by building a second pseudo-random test case having a second sequence of seeds comprising a second starting seed and a second ending seed through the test case generator system when the test case generator system is operating in a reproduction mode, the first starting seed being used as the second starting seed of the second sequence of seeds; and comparing the first ending seed in the first sequence of seeds to the second ending seed in the second sequence of seeds.Type: GrantFiled: February 28, 2008Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventor: Ali Y. Duale
-
Publication number: 20090222696Abstract: A method for monitoring a test case generator system by detecting non-reproducible pseudo-random test cases, comprising: building a first pseudo-random test case having a first sequence of seeds comprising a first starting seed and a first ending seed through the test case generator system; reproducing the first sequence of seeds of the first pseudo-random test case by building a second pseudo-random test case having a second sequence of seeds comprising a second starting seed and a second ending seed through the test case generator system when the test case generator system is operating in a reproduction mode, the first starting seed being used as the second starting seed of the second sequence of seeds; and comparing the first ending seed in the first sequence of seeds to the second ending seed in the second sequence of seeds.Type: ApplicationFiled: February 28, 2008Publication date: September 3, 2009Applicant: International Business Machines CorporationInventor: Ali Y. Duale
-
Publication number: 20080263121Abstract: A method of performing floating-point conversions in a digital computing system includes determining a source coefficient, c1, and a source exponent, n, of an input value represented by a floating-point number in a source base, b1; converting the source coefficient to a common base, b2, and storing the converted coefficient in a first digit collection; iteratively multiplying the contents of the first digit collection by b1 and storing the intermediate results therein, wherein one or more overflow bits of the first digit collection are carried and added to one or more additional digit collections once a nonzero value is reached; and an output value in the common base is stored in the digit collections after n multiplication iterations, represented by c2×b2m, wherein c2 is the converted coefficient of the output value in the common base b2 and m is the exponent of the output value.Type: ApplicationFiled: April 17, 2007Publication date: October 23, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Trevor E. Carlson, Ali Y. Duale
-
Publication number: 20080263120Abstract: A method of streamlining floating-point conversions includes determining a source coefficient and a source exponent of an input value represented by a floating-point number in a source base; estimating an approximated target exponent (ATE) using the source coefficient and the source exponent, in the event the source coefficient has a non-zero value; determining whether the ATE exceeds a maximum exponent so as to result an overflow, and outputting a predefined overflow value in the event of an overflow; determining whether the ATE exceeds a minimum exponent so as to result an underflow, and outputting a predefined underflow value in the event of an underflow; and in the event the ATE does not result in either an overflow or underflow, converting the input value to an output value represented by a converted coefficient, a converted base and the exponent of the output value.Type: ApplicationFiled: May 21, 2007Publication date: October 23, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Trevor E. Carlson, Ali Y. Duale
-
Publication number: 20080141084Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.Type: ApplicationFiled: January 30, 2008Publication date: June 12, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodore J. Bohizic, Ali Y. Duale, Dennis W. Wittig
-
Publication number: 20080141080Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.Type: ApplicationFiled: January 30, 2008Publication date: June 12, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodore J. Bohizic, Ali Y. Duale, Dennis W. Wittig