Patents by Inventor Alice E. White

Alice E. White has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210290949
    Abstract: Implantable nerve cuffs and methods for constructing or manufacturing the same are provided. Also provided is a method for installing a nerve into a nerve passage in the nerve cuff and a system using the nerve cuff. The nerve cuff is configured to retain one or more signal carrying elements such as electrodes proximal to a peripheral nerve in a human or animal subject. The nerve cuff may be constructed using a 3D printing method.
    Type: Application
    Filed: July 27, 2017
    Publication date: September 23, 2021
    Applicants: GALVANI BIOELECTRONICS LIMITED, TRUSTEES OF BOSTON UNIVERSITY
    Inventors: Bradley J. HOLINSKI, Timothy GARDNER, Charles A. LISSANDRELLO, Alice E. WHITE, Winthrop GILLIS, Jun SHEN, Timothy OTCHY, Christos MICHAS
  • Patent number: 11084215
    Abstract: A method for fabricating an electrode includes forming a 3D shell having a hollow interior and defining one or more openings, and directing an electrically conductive liquid through at least one of the one or more openings of the 3D shell, such that the 3D shell is at least partially filed with the electrically conductive liquid. The electrically conductive liquid can be caused to solidify within the 3D shell to form a solid electrode, or can remain a liquid to form a liquid electrode. The 3D shell can be formed having the one or more openings using a 3D printing process such as a two-photon writing system. The surface tension of the electrically conductive liquid aids in retaining the electrically conductive liquid within the 3D shell. The electrode can contact a tissue sample through one of the openings in the 3D shell.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: August 10, 2021
    Assignee: TRUSTEES OF BOSTON UNIVERSITY
    Inventors: Christopher S. Chen, Subramanian Sundaram, Christos Michas, Alice E. White, David J. Bishop
  • Publication number: 20200298490
    Abstract: A method for fabricating an electrode includes forming a 3D shell having a hollow interior and defining one or more openings, and directing an electrically conductive liquid through at least one of the one or more openings of the 3D shell, such that the 3D shell is at least partially filed with the electrically conductive liquid. The electrically conductive liquid can be caused to solidify within the 3D shell to form a solid electrode, or can remain a liquid to form a liquid electrode. The 3D shell can be formed having the one or more openings using a 3D printing process such as a two-photon writing system. The surface tension of the electrically conductive liquid aids in retaining the electrically conductive liquid within the 3D shell. The electrode can contact a tissue sample through one of the openings in the 3D shell.
    Type: Application
    Filed: March 19, 2020
    Publication date: September 24, 2020
    Inventors: Christopher S. Chen, Subramanian Sundaram, Christos Michas, Alice E. White, David J. Bishop
  • Patent number: 5122479
    Abstract: Disclosed is a method of making a Si-based semiconductor device comprising a contact region that comprises a thin (exemplarily less than 50 nm), substantially uniform silicide layer. The silicide preferably is CoSi.sub.2 or TiSi.sub.2. The method comprises implantation of the appropriate metal ions into a Si body, the dose and the body temperature selected such that substantially complete amorphization of the implant volume results. Subsequently, the Si body is subjected to an annealing treatment that results in recrystallization of the implant volume and formation of the silicide layer. The layer extends to the surface of the body and contains essentially all of the implanted metal ions. The invention can advantageously be used in conjunction with extremely shallow junctions, such as will be of interest in short (e.g., <0.5 .mu.m) channel CMOS devices.
    Type: Grant
    Filed: April 11, 1991
    Date of Patent: June 16, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: Sarah A. Audet, Conor S. Rafferty, Kenneth T. Short, Alice E. White
  • Patent number: 5053383
    Abstract: The critical current density J.sub.c of a superconductive oxide film can be tailored, without substantial change in the critical temperature T.sub.c (R.dbd.0), by introduction of radiation damage into the superconductor. Exemplarily, this is done by exposure to energetic (e.g., 1 MeV) ions. The ability to tailor J.sub.c permits optimization of SQUIDS and other thin film devices, and makes it possible to produce superconductive interconnects that comprise "fuses" or current limiters.
    Type: Grant
    Filed: March 29, 1988
    Date of Patent: October 1, 1991
    Assignee: AT&T Bell Laboratories
    Inventors: Kenneth T. Short, Alice E. White
  • Patent number: 4816421
    Abstract: Disclosed is a technique, termed "mesotaxy", for producing a heteroepitaxial structure comprising a layer of single crystal second material embedded in, and epitaxial with, a single crystal first material matrix. Mesotaxy comprises implantation of at least one chemical species (e.g., Co, Ni, Cr, Y or Mg) into a single crystal body (typically a semiconductor, e.g., Si or Ge) such that a buried layer rich in the implanted species is formed, and heat treating the implanted body such that a buried stoichiometric compound layer (e.g., CoSi.sub.2) is formed. Exemplarily, 3.multidot.10.sup.17 /cm.sup.2 200 keV Co ions are implanted into (100) Si nominally at 350.degree. C., followed by a heat treatment that consists of 1 hour at 600.degree. C. and 30 minutes at 1000.degree. C. The resulting buried CoSi.sub.2 layer is epitaxial with the Si matrix, has high conductivity and is of good crystalline quality. The Si overlayer is of device quality.
    Type: Grant
    Filed: November 24, 1986
    Date of Patent: March 28, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Robert C. Dynes, Kenneth T. Short, Alice E. White
  • Patent number: 4749660
    Abstract: We have discovered that high quality subcritical SIMOX silicon-on-insulator wafers can be produced by a method that comprises a randomizing implant followed by an appropriate heat treatment. In a preferred embodiment, the inventive method comprises, in succession, a subcritical oxygen implant (nominal wafer temperature <350.degree. C.) into a (100) Si wafer, a low temperature (500.degree.-700.degree. C.) anneal, a high temperature (>1200.degree. C.) anneal, a randomizing implant (.about.5.times.10.sup.14 Si/cm.sup.2, nominal wafer temperature <100.degree. C.), and a low temperature anneal (nominal wafer temperature between 500.degree. and 700.degree. C.). The resulting buried SiO.sub.2 layer typically is relatively thin (e.g., 60 nm), stoichiometric, continuous, and essentially free of Si inclusions, and the Si overlayer typically is of device quality and essentially free of twins, with .chi.min.about.3%.
    Type: Grant
    Filed: November 26, 1986
    Date of Patent: June 7, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Kenneth T. Short, Alice E. White