Patents by Inventor Alice Hwajin Lee

Alice Hwajin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Noise impact on function (NIOF) reduction for integrated circuit design
    Patent number: 11875099
    Abstract: Examples described herein provide a computer-implemented method that includes identifying, by a processing device, a victim/aggressor pair of nets for an integrated circuit. The method further includes severing nets of the victim/aggressor pair of nets. The method further includes swapping severed segments of the nets. The method further includes rerouting the nets subsequent to swapping the severed segments of the nets.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: January 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Gerald L Strevig, III, Adam P. Matheny, Alice Hwajin Lee, Jose Luis Pontes Correia Neves
  • NOISE IMPACT ON FUNCTION (NIOF) REDUCTION FOR INTEGRATED CIRCUIT DESIGN
    Publication number: 20230038399
    Abstract: Examples described herein provide a computer-implemented method that includes identifying, by a processing device, a victim/aggressor pair of nets for an integrated circuit. The method further includes severing nets of the victim/aggressor pair of nets. The method further includes swapping severed segments of the nets. The method further includes rerouting the nets subsequent to swapping the severed segments of the nets.
    Type: Application
    Filed: August 9, 2021
    Publication date: February 9, 2023
    Inventors: Gerald L. Strevig, III, Adam P. Matheny, Alice Hwajin Lee, Jose Luis Pontes Correia Neves
  • Single-bit latch optimization for integrated circuit (IC) design
    Patent number: 10878152
    Abstract: Techniques for an IC design include placing latches between a source and one or more sinks in the IC design, and performing an iterative process for maximizing slack on one or more input nets and one or more output nets for each of the latches, minimizing an absolute difference of the slack. The IC design includes optimizing routing for the latches and placing a clock gating latch in the IC design designated to control a LCB of LCBs. The IC design includes placing LCB logic in the IC design to control a required number of the LCBs, and placing a local clock buffer controller in the IC design in proximity to the positions of the latches.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: December 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jose Neves, Adam Matheny, Alice Hwajin Lee