Abstract: A single chip adaptive filtering system including an finite impulse response (FIR) filter and circuitry for calculating updated weighting coefficients for use in associated multiplying digital-to-analog converters. The adaptive FIR filter performs the convolution of a delayed and sampled input sequence to produce a filter output. Thereafter, an error term is determined by calculating the difference between the filter output and a reference signal which corresponds to a predetermined anticipated output of the filter. The error term is then applied to a least mean square (LMS) estimation algorithm for computing updated weighting coefficients to be used by the adaptive FIR filter.

Abstract: A three dimensional (3D) discrete cosine transform (DCT) uses one dimensional DCT networks for transforming and inverse-transforming blocks of data, such as image data. The 3D DCT configuration uses DCT transform coding to remove both the spatial and temporal redundancy of a sequence of image frames to achieve high bandwidth compression.

Abstract: A charge domain vector-matrix product processing system. The system includes a charge coupled device tapped delay line, an array of digital parallel shift register memory devices, and a signal processor. A sampled analog signal is stored within the tapped delay line, and multiple vectors of m-bit words are stored within the digital memory device. The signal processor sucessively applies vectors from the digital memory device and charge packets from the tapped delay line to an array of digital-analog multipliers. The signal processor then sums the outputs of the digital-analog multipliers and produces an output charge packet corresponding to a respective element of the vector-matrix product.

Abstract: A full search block matching algorithm includes a charge-domain serial tapped delay line as an input buffer, and an array of charge domain signal processors. The delay line shifts and holds analog sampled data which are in the form of charge packets. At each stage of delay, the signals are nondestructively sensed and coupled to a corresponding signal processor, and the sampled data are transferred and subsequently processed in parallel. The processed data from all the processors can be read out either in a parallel or serial format through a parallel-in-serial-out output buffer. In this structure, only the serial input buffer has to be clocked at the system throughout rate; the internal clock rate of each processor is reduced by the number of parallel processors. Within each processor, all of the computation functions are performed in the charge domain, and local charge domain memories are included for storing the processed signal.

Abstract: A charge domain parallel processing network. The network includes a floating gate CCD tapped delay line and an array of CCD signal processors each including a charge domain digital-analog multiplier. The delay line holds and shifts analog sampled data in the form of charge packets. At each stage of the delay line a floating gate sensing electrode is coupled to an analog input of an associated one of the CCD signal processors. The sampled data in the respective delay line stages are transferred and subsequently processed in parallel in the processors. Within each processor, the computation functions are performed in the charge domain. In some forms, local charge domain accumulating memories accumulate and store the processed signals, for example, providing a matrix-matrix product network or providing a triple-matrix product network.

Abstract: A charge domain digital-analog multiplier device. The device has one analog input, M-parallel digital inputs, and one analog output. An M-bit digital word signal is applied to the digital inputs and an analog signal is applied to the analog input. The output is a charge packet which is proportional to the product of the analog input signal and the digital word.

Abstract: A photodiode detector apparatus having a Gallium Phosphide ion implantation junction thereon to provide high quantum efficiency at wavelengths equal to or less than 0.5 micron incident wavelength while utilizing a shallow junction.

Abstract: A gallium phosphide metal semiconductor field-effect transistor (MESFET) or a junction field-effect transistor (JFET) exhibits very low leakage current, is radiation hard, and is capable of high operating temperatures.

Abstract: A pyroelectric detector as formed by parylene C polymer film.

Abstract: An ultraviolet sensitive photodiode is formed in a body of first conductivity type GaP. A region of second conductivity type with a graded impurity distribution is formed in the body, and a thin layer (preferably about 100A to 300A) is then removed from the front surface of the body. The removal of the thin layer significantly enhances the performance of the UV sensitive photodiode.

Abstract: A GaP photodiode having a shallow PN junction and an internal directed surface electric field exhibits high quantum efficiency in detecting ultraviolet wavelengths.

Abstract: Pyroelectric detectors are mounted on a substrate having a plurality of wax-filled cavities. The wax is then dissolved to provide a low thermal loss mounting structure for the detectors.