Abstract: A method of forming an ATM cell having a fixed length from CPS packets according to the AAL2 protocol includes the steps of placing a header at a beginning of the ATM cell and then packing the ATM cell with the payload of the CPS packets. ATM cells are formed until the payload of the last CPS packet has been packed into an ATM cell. A TimerCU is not triggered until the last available CPS packet has been processed. If the last ATM cell formed is not full, it is padded until it is full.

Abstract: A method of forming an ATM cell having a fixed length from CPS packets according to the AAL2 protocol includes the steps of placing a header at a beginning of the ATM cell and then packing the ATM cell with the payload of the CPS packets. ATM cells are formed until the payload of the last CPS packet has been packed into an ATM cell. A TimerCU is not triggered until the last available CPS packet has been processed. If the last ATM cell formed is not full, it is padded until it is full.

Abstract: A clock system (2) for providing a system clock signal at a clock output (4) for use by a processing unit comprises a first oscillator circuit (6) which is enabled in response to a wake up signal provided by the processing unit to provide a first clock signal (RINGO CLOCK) at an output, and a second oscillator circuit (8) comprising a PLL (14) and an oscillator (16). The second oscillator (8) circuit provides a second clock signal (PLL CLOCK) and a lock signal (LOCKED) at first and second outputs respectively when the PLL is locked.

Abstract: A mantissa addition system (2) having a mantissa adder (6) for adding two mantissas provides an addition result a plurality of bits arranged in sub-groups. The mantissa addition system also has a flag generator which generates a flag for each sub-group: each flag having an active state when all the bits in the respective sub-group are zero and an inactive state when at least one of the bits in the respective sub-group is non-zero. A first detector (46) determines the most significant flag that has the inactive state and provides a first control signal representative of the detected most significant flag. A first shifter (40) shifts the groups of bits of the addition result in response to the first control signal so that the sub-group of bits corresponding to the detected most significant flag is the most significant group.