Patents by Inventor Alireza Kasnavi
Alireza Kasnavi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8924906Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.Type: GrantFiled: September 3, 2013Date of Patent: December 30, 2014Assignee: Synopsys, Inc.Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi, Subramanyam Sripada
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Publication number: 20140059508Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.Type: ApplicationFiled: September 3, 2013Publication date: February 27, 2014Applicant: Synopsys, Inc.Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi, Subramanyam Sripada
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Patent number: 8478573Abstract: A model for a circuit cell used in timing and signal integrity analysis in an integrated circuit design is automatically generated. A behavioral model, such as a gate current model is used in which the current in the circuit cell is determined as a function of the input voltage and the output voltage of the circuit cell as well as the history of at least one of the current, voltage, and charge values of the circuit cell. For example, the current in the circuit cell may be a function of the history of the current, which may be calculated incrementally using recursive convolution at each time step when using the model.Type: GrantFiled: June 23, 2005Date of Patent: July 2, 2013Assignee: Synopsys, Inc.Inventors: Li Ding, Peivand Fallah-Tehrani, Alireza Kasnavi
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Patent number: 8418103Abstract: Circuit behaviors are scaled to different operating conditions by using a generalized nonlinear model. Nonlinear transforms are applied to the operating conditions and/or to the circuit behaviors contained in a library set. The transformed quantities have a more linear relationship between them. Parameters for the linear relationship are estimated based on the data and operating conditions in the library set. These parameters and nonlinear transforms can then be used to scale circuit behaviors to operating points not contained in the library set.Type: GrantFiled: July 28, 2011Date of Patent: April 9, 2013Assignee: Synopsys, Inc.Inventors: Xin Wang, Alireza Kasnavi
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Patent number: 8341574Abstract: Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to calculate the total time delay in a signal path due to crosstalk from a group of crosstalk aggressors that are associated with a group of signal paths. In order to properly account for statistical behaviors in the switching times and directions of the switching patterns in the group of signal paths, the time-delay contribution from each of these crosstalk aggressors may be modeled as a corresponding statistical random variable. Because the number of crosstalk aggressors are usually much larger than the number of stages in the signal path, the calculated total path delay may be less pessimistic. Furthermore, in order to detect potential timing violations, the time-delay contributions from additional dominant crosstalk aggressors can be modeled using non-statistical worst-case deterministic values.Type: GrantFiled: March 6, 2009Date of Patent: December 25, 2012Assignee: Synopsys, Inc.Inventors: Ravikishore Gandikota, Li Ding, Peivand Tehrani, Nahmsuk Oh, Alireza Kasnavi
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Publication number: 20120079441Abstract: Circuit behaviors are scaled to different operating conditions by using a generalized nonlinear model. Nonlinear transforms are applied to the operating conditions and/or to the circuit behaviors contained in a library set. The transformed quantities have a more linear relationship between them. Parameters for the linear relationship are estimated based on the data and operating conditions in the library set. These parameters and nonlinear transforms can then be used to scale circuit behaviors to operating points not contained in the library set.Type: ApplicationFiled: July 28, 2011Publication date: March 29, 2012Applicant: SYNOPSYS, INC.Inventors: Xin Wang, Alireza Kasnavi
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Patent number: 8145442Abstract: Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to analyze an electrical characteristic of a logic gate electrically coupled to an output network in a stage. In particular, during the analysis, the effective capacitance of an output network coupled to a logic gate is approximated as a function of a total resistance of the output network, a total capacitance of the output network, and a geometric parameter of the output network. Using the effective capacitance and other parameters, such as a slew rate of an electrical signal applied to an input of the logic gate, an electrical characteristic of the logic gate, such as an input capacitance, is determined.Type: GrantFiled: January 30, 2009Date of Patent: March 27, 2012Assignee: Synopsys, Inc.Inventors: Hong Li, Li Ding, Alireza Kasnavi
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Patent number: 7962876Abstract: Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.Type: GrantFiled: October 31, 2008Date of Patent: June 14, 2011Assignee: Synopsys, Inc.Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi
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Publication number: 20110113396Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.Type: ApplicationFiled: January 17, 2011Publication date: May 12, 2011Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi, Subramanyam Sripada
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Patent number: 7900165Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.Type: GrantFiled: March 30, 2007Date of Patent: March 1, 2011Assignee: Synopsys, Inc.Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi, Subramanyam Sripada
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Patent number: 7861198Abstract: A method to perform timing analysis for a complex logic cell with distorted input waveform and coupled load networks is presented. Timing arc based models are used in conjunction with CCB based current models of portions of the logic cell to compute the output signal of the logic cell. For example, an intermediary signal is generated using a first timing arc based model and an equivalent coupled network output signal is generated using a channel connected block (CCB) based current model.Type: GrantFiled: September 28, 2007Date of Patent: December 28, 2010Assignee: Synopsys, Inc.Inventors: Li Ding, Peivand Tehrani, Jindrich Zejda, Alireza Kasnavi
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Publication number: 20100229136Abstract: Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to calculate the total time delay in a signal path due to crosstalk from a group of crosstalk aggressors that are associated with a group of signal paths. In order to properly account for statistical behaviors in the switching times and directions of the switching patterns in the group of signal paths, the time-delay contribution from each of these crosstalk aggressors may be modeled as a corresponding statistical random variable. Because the number of crosstalk aggressors are usually much larger than the number of stages in the signal path, the calculated total path delay may be less pessimistic. Furthermore, in order to detect potential timing violations, the time-delay contributions from additional dominant crosstalk aggressors can be modeled using non-statistical worst-case deterministic values.Type: ApplicationFiled: March 6, 2009Publication date: September 9, 2010Applicant: SYNOPSYS, INC.Inventors: Ravikishore Gandikota, Li Ding, Peivand Tehrani, Nahmsuk Oh, Alireza Kasnavi
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Publication number: 20100198539Abstract: Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to analyze an electrical characteristic of a logic gate electrically coupled to an output network in a stage. In particular, during the analysis, the effective capacitance of an output network coupled to a logic gate is approximated as a function of a total resistance of the output network, a total capacitance of the output network, and a geometric parameter of the output network. For example, the effective capacitance may be approximated as a function of a ratio of the product of the total resistance and the total capacitance to the fanout count of the output network. Using the effective capacitance and other parameters, such as a slew rate of an electrical signal applied to an input of the logic gate, an electrical characteristic of the logic gate, such as an input capacitance, is determined.Type: ApplicationFiled: January 30, 2009Publication date: August 5, 2010Applicant: SYNOPSYS, INC.Inventors: Hong Li, Li Ding, Alireza Kasnavi
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Publication number: 20090089729Abstract: A method to perform timing analysis for a complex logic cell with distorted input waveform and coupled load networks is presented. Timing arc based models are used in conjunction with CCB based current models of portions of the logic cell to compute the output signal of the logic cell. For example, an intermediary signal is generated using a first timing arc based model and an equivalent coupled network output signal is generated using a channel connected block (CCB) based current model.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Inventors: Li Ding, Peivand Tehrani, Jindrich Zejda, Alireza Kasnavi
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Publication number: 20090055787Abstract: Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.Type: ApplicationFiled: October 31, 2008Publication date: February 26, 2009Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi
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Patent number: 7454731Abstract: Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.Type: GrantFiled: September 22, 2006Date of Patent: November 18, 2008Assignee: Synopsys, Inc.Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi
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Publication number: 20080243414Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: Synopsys, Inc.Inventors: Nahmsuk Oh, Peivand Fallah-Tehrani, Alireza Kasnavi, Subramanyam Sripada
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Publication number: 20080077900Abstract: Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.Type: ApplicationFiled: September 22, 2006Publication date: March 27, 2008Inventors: Nahmsuk Oh, Pelvand Fallah-Tehrani, Alireza Kasnavi
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Patent number: 7272807Abstract: An equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated. The equivalent waveform is produced by calculating the transition quantity of a first non-distorted waveform. The transition quantity is the amount of transition of the first non-distorted waveform that is required for the cell to produce an output waveform with a predetermined end voltage. The end point of the transition period for the distorted waveform is then determined based on when the distorted waveform has accumulated the same transition quantity. The equivalent waveform can then be formed by computing a second non-distorted waveform such that the end point of the transition period for the second non-distorted waveform coincides with the end point of the transition period for the distorted waveform.Type: GrantFiled: March 2, 2005Date of Patent: September 18, 2007Assignee: Synopsys, Inc.Inventors: Li Ding, Peivand Fallah Tehrani, Alireza Kasnavi
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Patent number: 7263676Abstract: One embodiment of the invention provides a system that analyzes the propagation of noise through an integrated circuit. During operation, the system obtains an input noise signal to be applied to a cell within the integrated circuit. The system then looks up parameters specifying how noise affects the cell, and then uses the parameters to determine how the input noise signal affects the cell. This can involve determining if the input noise signal will cause the cell to fail and/or determining a propagated noise signal that emanates from the cell.Type: GrantFiled: April 9, 2003Date of Patent: August 28, 2007Assignee: Synopsys, Inc.Inventors: Alexander Gyure, Jindrich Zejda, Peivand Fallah-Tehrani, Wenyuan Wang, Chi-Chong Lo, Seyed Alireza Kasnavi, Mahmoud Shahram, Yansheng Luo, William Chiu-Ting Shu