Abstract: A technique for reducing leakage current in static CMOS devices by adding additional transistors in series between selected inverters or logic gates and ground or power. NMOS and PMOS transistors are added to selected buffers comprised of two inverters in series. The PMOS transistor is connected between the first inverter and power and the NMOS transistor is connected between the second inverter and ground. The added transistors are controlled by a memory cell to be on when the buffer is being used and off when the buffer is unused. Alternatively, no PMOS transistor is added and an existing PMOS transistor of the first inverter is manufactured to sit in a Vgg well. The same techniques are employed with selected buffer pairs and logic gates.

Abstract: An apparatus for implementing fast sum-of-products logic in an FPGA is disclosed. The apparatus includes a CLB including a plurality of slices and a second-level logic circuit to combine the outputs of the slices. Typically, the second-level logic circuit is an OR gate or its equivalent that implements the sum portion of the sum-of-products expression. Alternatively, a combining gate may be included within the slice to combine the output of one slice with the output of another slice. In this case the combing gates of each of the slices are connected in series to sum the result of the product operation of a given slice with the product operations from preceding slices. The slice may also include a dedicated function generator to increase the performance of each slice to implement wide functions, particularly sum-of-products functions. The dedicated function generator may include an AND gate and an OR gate with a multiplexer as a selector.

Abstract: A programmable monolithic integrated logic circuit that includes look up table circuits and programmable logic array-like circuits. The integrated circuit can include a first number of the look up tables and a second number of the programmable logic array-like circuits and where the first and second numbers are related by a ratio of between 0.25:1 and 6:1, between 1:1 and 5:1, or about 4:1. The programmable logic array-like circuits can each include at least 10,000 or 50,000 equivalent two-input NAND gates, and the look up tables and the programmable logic array-like circuits can each comprise static random access cells. A method of implementing a logic circuit includes reading a netlist that includes a plurality of subnets.

Abstract: A computational field programable architecture targeted for compute intensive applications. The architecture is hierarchical and includes, for implementation of data path circuits, clusters of programable logic blocks that are designed to provide area-efficient realization of common arithmetic structures such as adders, subtracters and multipliers. The architecture includes a LUTb cluster for implementing the control part of a circuit. The programable logic blocks each include a stack of programable bit-slice logic elements each having 2 data inputs and a single data output, and a 1-bit full adder circuit. The bit slice logic elements allow bit-wise logic operations to be carried out and the programable logic blocks also include comparator logic to enable comparison operations to be performed. The bit slice logic elements each include a DFF at their output, and the DFFs in a programable logic blocks can be combined to form a register.

Abstract: A programmable monolithic integrated logic circuit that includes look up table circuits and programmable logic array-like circuits. The integrated circuit can include a first number of the look up tables and a second number of the programmable logic array-like circuits and where the first and second numbers are related by a ratio of between 0.25:1 and 6:1, between 1:1 and 5:1, or about 4:1. The programmable logic array-like circuits can each include at least 10,000 or 50,000 equivalent two-input NAND gates, and the look up tables and the programmable logic array-like circuits can each comprise static random access cells. A method of implementing a logic circuit includes reading a netlist that includes a plurality of subnets.