Patents by Inventor Alisa Yurovsky

Alisa Yurovsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MODIFIED PROTEIN ENCODING SEQUENCES HAVING INCREASED RARE HEXAMER CONTENT
    Publication number: 20190169235
    Abstract: This invention provides a modified protein encoding sequence containing nucleotide substitutions at multiple locations in the protein encoding sequence, wherein the substitutions introduce rare hexamers. These hexamers may be Frame Dependent, or depleted in only the reading frame, or Frame Independent, or depleted in all three frames. Modified protein encoding se quences of the present invention may include modified viruses useful for vaccines.
    Type: Application
    Filed: November 7, 2016
    Publication date: June 6, 2019
    Inventors: Bruce Futcher, Justin Gardin, Steven Skiena, Alisa Yurovsky, Eckard Wimmer, Steffen Mueller
  • Optimizing circuit layouts by configuring rooms for placing devices
    Patent number: 8527928
    Abstract: A computer-readable medium stores a specification for a circuit layout. The specification includes: a configuration of rooms for placing devices, one or more room constraints for the configuration of rooms, one or more groups of devices for the rooms, and one or more device constraints for devices in a same room. The configuration of rooms may include a tree-structure for the rooms. The room constraints may include a common symmetry line for a first room and a second room. The device constraints may include a self-symmetry constraint for a first device about a symmetry line in a first room. The device constraints may include a symmetry constraint for a first device and a second device about a symmetry line in a first room. The devices may include analog or RF (radio frequency) devices.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: September 3, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Prakash Gopalakrishnan, Alisa Yurovsky
  • Registry for electronic design automation of integrated circuits
    Patent number: 7945890
    Abstract: A method for registering constraints for EDA (Electronic Design Automation) of an IC (Integrated circuit) includes: associating a constraint with values for constraint identification that identify the constraint in an IC design; associating the constraint with values for constraint relationships that relate the constraint to at least one EDA application; saving the constraint identification values and the constraint relationship values in a constraint registry element; and providing an interface to a user for accessing values of the constraint registry element.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 17, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Regis Colwell, Gilles S. C. Lamant, Alisa Yurovsky, Timothy Rosek
  • Optimizing circuit layouts by configuring rooms for placing devices
    Patent number: 7665054
    Abstract: A computer-readable medium stores a specification for a circuit layout. The specification includes: a configuration of rooms for placing devices, one or more room constraints for the configuration of rooms, one or more groups of devices for the rooms, and one or more device constraints for devices in a same room. The configuration of rooms may include a tree-structure for the rooms. The room constraints may include a common symmetry line for a first room and a second room. The device constraints may include a self-symmetry constraint for a first device about a symmetry line in a first room. The device constraints may include a symmetry constraint for a first device and a second device about a symmetry line in a first room. The devices may include analog or RF (radio frequency) devices.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: February 16, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Prakash Gopalakrishnan, Alisa Yurovsky
  • REGISTRY FOR ELECTRONIC DESIGN AUTOMATION OF INTEGRATED CIRCUITS
    Publication number: 20090113369
    Abstract: A method for registering constraints for EDA (Electronic Design Automation) of an IC (Integrated circuit) includes: associating a constraint with values for constraint identification that identify the constraint in an IC design; associating the constraint with values for constraint relationships that relate the constraint to at least one EDA application; saving the constraint identification values and the constraint relationship values in a constraint registry element; and providing an interface to a user for accessing values of the constraint registry element.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 30, 2009
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Regis Colwell, Gilles S.C. Lamant, Alisa Yurovsky, Timothy Rosek