Abstract: Superconducting circuit with virtual timing elements and related methods are described. A method includes specifying a superconducting circuit portion including a timing path comprising: (1) at least one logic gate to be implemented using Josephson junctions, (2) a first virtual timing element for defining a synchronization point along the timing path, and (3) a second virtual timing element for adding latency to the timing path. The method further includes synthesizing the superconducting circuit portion, where the synthesizing comprises treating the first virtual timing element as a first flip-flop and the second virtual timing element as a second flip-flop, where the first flip-flop is treated as being fixed in relation to the at least one logic gate along the timing path, but the second flip-flop is treated as being movable in relation to the at least one logic gate along the timing path.

Abstract: Superconducting circuit with virtual timing elements and related methods are described. A method includes specifying a superconducting circuit portion including a timing path comprising: (1) at least one logic gate to be implemented using Josephson junctions, (2) a first virtual timing element for defining a synchronization point along the timing path, and (3) a second virtual timing element for adding latency to the timing path. The method further includes synthesizing the superconducting circuit portion, where the synthesizing comprises treating the first virtual timing element as a first flip-flop and the second virtual timing element as a second flip-flop, where the first flip-flop is treated as being fixed in relation to the at least one logic gate along the timing path, but the second flip-flop is treated as being movable in relation to the at least one logic gate along the timing path.

Abstract: Interface processor (IP)(50) sends and receives data units to and from an external host and a processor. The IP is capable of simultaneous, full duplex operation via high speed serial and parallel interfaces. The IP provides a highly flexible and configurable interface which is capable of interfacing to a variety of systems with minimal external hardware. The IP also provides a method of converting received data into data packets. The IP provides buffering of multiple data packets for use in systems having "bursty" data traffic. The IP has a memory expansion capability allowing for changeable buffer capacities.