Abstract: A system, method, and apparatus are provided for processing packets received over Controller Area Network (CAN) interface where a CAN protocol controller computes a CRC value from header and payload values in a received CAN data frame to verify frame integrity of the received CAN data frame across a physical media layer, and then stores the header and payload values and the CRC value in a memory buffer of the CAN protocol controller so that a host core can compute a reconstructed CRC value from the header and payload values retrieved from the memory buffer, and then compare the reconstructed CRC value to the CRC value retrieved from the memory buffer to verify frame integrity of the received CAN data frame at a transaction layer.

Abstract: A system, method, and apparatus are provided for processing packets received over Controller Area Network (CAN) interface where a CAN protocol controller computes a CRC value from header and payload values in a received CAN data frame to verify frame integrity of the received CAN data frame across a physical media layer, and then stores the header and payload values and the CRC value in a memory buffer of the CAN protocol controller so that a host core can compute a reconstructed CRC value from the header and payload values retrieved from the memory buffer, and then compare the reconstructed CRC value to the CRC value retrieved from the memory buffer to verify frame integrity of the received CAN data frame at a transaction layer.

Abstract: A processing system comprising a first processing domain and a second processing domain. Each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core. The processing system further comprises a supervisor component arranged to receive the sets of internal state signals output by the processor cores of the first and second processing domains, compare internal state signals output by the processor core of the first processing domain to corresponding internal state signals output by the processor core of the second processing domain, and upon detection of a mismatch between compared internal state signals to initiate a reset of a thread under the execution of which the detected mismatch of internal state signals occurred.

Abstract: A processing system comprising a first processing domain and a second processing domain. Each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core. The processing system further comprises a supervisor component arranged to receive the sets of internal state signals output by the processor cores of the first and second processing domains, compare internal state signals output by the processor core of the first processing domain to corresponding internal state signals output by the processor core of the second processing domain, and upon detection of a mismatch between compared internal state signals to initiate a reset of a thread under the execution of which the detected mismatch of internal state signals occurred.

Abstract: An error response method for a mixed criticality system includes assigning a safety level to an application executed by a processor. Executing the application includes a transaction between the processor and a resource. The safety level is stored at the resource. The safety level and a fault indication are transmitted from the resource to a fault collection and control unit (FCCU). The fault indication is responsive to a fault from the resource. The FCCU responds to the fault indication with an action determined by the safety level.

Abstract: An error response method for a mixed criticality system includes assigning a safety level to an application executed by a processor. Executing the application includes a transaction between the processor and a resource. The safety level is stored at the resource. The safety level and a fault indication are transmitted from the resource to a fault collection and control unit (FCCU). The fault indication is responsive to a fault from the resource. The FCCU responds to the fault indication with an action determined by the safety level.