Abstract: An adaptor circuit 20 for peripheral devices 14, 18 is provided with a direct memory access manager 38. This local direct memory access manager 38 is able to autonomously manage data transfers on behalf of its associated peripheral device 14, 18. A computer program tools used to generate signal interconnects 24 is used to additionally specify whether a DMA capability is to be provided for a peripheral device 14, 18, whereupon an adaptor circuit 20, 22 including a DMA manager 38 can be included within the signal interconnect. A DMA command signal is added to the interconnect signals being passed around the signal interconnect 24 and enables DMA command/configuration data to be distributed using the existing signal distribution infrastructure and addressed to the associated peripheral device 14, 18 of the target local DMA controller 38.

Abstract: A data processing apparatus and method of arbitration within such a data processing apparatus are provided for arbitrating between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit of that data processing apparatus. The plurality of paths include a shared connection, the data processing apparatus having a plurality of initiator logic elements for initiating transfers and a plurality of recipient logic elements for receiving transfers, for each transfer the corresponding path coupling the initiator logic element responsible for initiating that transfer with the recipient logic element destined to receive that transfer. At least one of the recipient logic elements that is destined to receive one of the transfers has a storage element associated therewith which is operable to temporarily store transfer data of that transfer.

Abstract: A data processing apparatus and method of arbitration within such a data processing apparatus are provided for arbitrating between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit of that data processing apparatus. The plurality of paths include a shared connection, the data processing apparatus having a plurality of initiator logic elements for initiating transfers and a plurality of recipient logic elements for receiving transfers, for each transfer the corresponding path coupling the initiator logic element responsible for initiating that transfer with the recipient logic element destined to receive that transfer. At least one of the recipient logic elements that is destined to receive one of the transfers has a storage element associated therewith which is operable to temporarily store transfer data of that transfer.