Patents by Inventor Alistair J. Gorman

Alistair J. Gorman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High capacity I/O (input/output) cells
    Patent number: 10094873
    Abstract: A wafer structure has a plurality of semiconductor die. Each semiconductor die includes circuitry, a test pad for use in testing the circuitry, and a plurality of external pins. The test pad includes first, second, third, and fourth metal lines, a via, and a metal cover that receives a probe. The first and second metal lines are in a first metal layer and run in parallel, are insulated from each other, and are adjacent. The third and fourth metal lines are in a second metal layer run in parallel, are insulated from each other, and run orthogonal to the first and second metal lines. The first via is coupled to the first metal line and the third metal line. One or more external pins are connected to the metal cover.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: October 9, 2018
    Assignee: NXP USA, Inc.
    Inventors: David R. Tipple, Alistair J. Gorman, Anis M. Jarrar
  • HIGH CAPACITY I/O (INPUT/OUTPUT) CELLS
    Publication number: 20170059650
    Abstract: A wafer structure has a plurality of semiconductor die. Each semiconductor die includes circuitry, a test pad for use in testing the circuitry, and a plurality of external pins. The test pad includes first, second, third, and fourth metal lines, a via, and a metal cover that receives a probe. The first and second metal lines are in a first metal layer and run in parallel, are insulated from each other, and are adjacent. The third and fourth metal lines are in a second metal layer run in parallel, are insulated from each other, and run orthogonal to the first and second metal lines. The first via is coupled to the first metal line and the third metal line. One or more external pins are connected to the metal cover.
    Type: Application
    Filed: August 28, 2015
    Publication date: March 2, 2017
    Inventors: David R. Tipple, Alistair J. Gorman, Anis M. Jarrar
  • Non-volatile memory with controlled program/erase
    Patent number: 7397703
    Abstract: A method for programming/erasing a non-volatile memory (NVM) includes performing a program/erase operation on a portion of the NVM using a first set of parameters. The method further includes determining whether each cell in the portion of the NVM passes a first margin level, if not determining which one of a set of lower margin levels than the first margin level each cell in the portion of the NVM passes. The method further includes modifying at least one of the set of parameters associated with a subsequent program/erase operation for the portion of the NVM based on the determined one of the set of lower margin levels.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: July 8, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Martin L. Niset, Derek J. Beattie, Andrew E. Birnie, Alistair J. Gorman, Stephen McGinty