Abstract: A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in parallel. In response to a task identifier being received that is indicative of a task requiring an improved level of determinism, the dual-issue capability of at least one of the first thread or the second thread is temporarily disabled.

Abstract: A system on chip, comprising a processing unit for executing processes, a memory unit, and a memory control unit connected between the processing unit and the memory unit, is described. The memory control unit allocates a memory region to a process. The memory control unit comprises a process activity counter which counts a duration of the process or transactions by the process to or from the memory region and which maintains a process activity count representing the counted duration of the process or the counted transactions to or from the memory region. The memory control unit disables the memory region in response to the process activity count exceeding a maximum process activity count. Notably, it blocks the memory region against further transactions by the process and against transactions by any other processes. A method of operating a system on chip is also described.

Abstract: A method of detecting overcurrent events within at least one electronic device, and an overcurrent detection module therefor. The method comprises receiving at least one current requirement indication from at least one electronic device, determining at least one overcurrent value based at least partly on the received at least one current requirement indication, receiving at least one indication of at least one input current flow for the at least one electronic device, and determining that an overcurrent event is occurring if the indicated at least one input current flow for the at least one electronic device exceeds the determined at least one overcurrent value.

Abstract: A processor system includes at least two processor cores and an interrupt controller including interrupt priority registers configured for registering interrupt priorities of the respective processor cores. The processor system further includes at least two task timers associated with respective processor cores. Each task timer includes a counter configured for producing a counter value, a timeout value register configured for storing a timeout value and a tidemark value register configured for storing a tidemark value smaller than the timeout value. Each task timer is configured for producing a timeout signal when the counter value equals the timeout value and for producing a tidemark signal when the counter value equals the tidemark value. The interrupt controller is configured for increasing the interrupt priority of a processor core in response to a tidemark signal and for decreasing the interrupt priority of a processor core in response to a timeout signal.

Abstract: An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. The technique may include providing a base address and a transfer trigger to initiate the transferring of the peripheral data. The technique may include executing a peripheral interrupt service routine after executing the interrupt service routine prologue. The technique may include executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including resetting an interrupt status flag associated with the interrupt request.

Abstract: A peripheral integrated circuit (IC) device for providing support to a data processing IC device. The peripheral IC device comprises a fault detection component arranged to detect an occurrence of fault conditions within the data processing IC device. The peripheral IC device further comprises a safe state control component. Upon detection of a fault condition occurring within the data processing IC device by the fault detection component, the safe state control component is arranged to cause at least one I/O cell of the data processing IC device to be configured into at least one scan-chain, and cause at least one predefined control signal to be scanned into the at least one scan-chain to configure the at least one I/O cell into a state corresponding to the predefined control signal.

Abstract: A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in parallel. In response to a task identifier being received that is indicative of a task requiring an improved level of determinism, the dual-issue capability of at least one of the first thread or the second thread is temporarily disabled.

Abstract: A method for providing memory protection within a signal processing system comprises receiving a memory access signal comprising at least one instruction memory region (IMR) indication. The IMR indication comprises an indication of a region of memory from which a memory access instruction was fetched, execution of said memory access instruction having resulted in the generation of the received memory access signal. The method further comprises comparing the IMR indication for the received memory access signal to at least one permitted memory region (PMR) indication for a target address of the received memory access signal, and determining whether a memory access being attempted by the memory access signal is permitted based at least partly on the comparison of the IMR indication for the received memory access signal to the PMR indication for the target address of the received memory access signal.

Abstract: An error response method for a mixed criticality system includes assigning a safety level to an application executed by a processor. Executing the application includes a transaction between the processor and a resource. The safety level is stored at the resource. The safety level and a fault indication are transmitted from the resource to a fault collection and control unit (FCCU). The fault indication is responsive to a fault from the resource. The FCCU responds to the fault indication with an action determined by the safety level.

Abstract: An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. The technique may include providing a base address and a transfer trigger to initiate the transferring of the peripheral data. The technique may include executing a peripheral interrupt service routine after executing the interrupt service routine prologue. The technique may include executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including resetting an interrupt status flag associated with the interrupt request.

Abstract: High frequency detection of interrupts includes incrementing a count by a first number in response to at least one interrupt. The count is decremented by a second number in response to a clock if the count is greater than zero. An interrupt rate is determined from the count. A fault collection unit (FCU) is updated when the interrupt rate exceeds a threshold.

Abstract: An error response method for a mixed criticality system includes assigning a safety level to an application executed by a processor. Executing the application includes a transaction between the processor and a resource. The safety level is stored at the resource. The safety level and a fault indication are transmitted from the resource to a fault collection and control unit (FCCU). The fault indication is responsive to a fault from the resource. The FCCU responds to the fault indication with an action determined by the safety level.

Abstract: In a system on chip SoC, a memory control unit connected between the memory unit and the processing unit controls access to the memory unit. An update request received or generated by the processing unit triggers an update operation which comprises appending an update enabling record to a sequence of update records in the log region, writing new program code to the memory unit, and appending an update completion record to a sequence of update records. Write access to the log region is disabled if a fault is detected in the SoC during the update operation.

Abstract: The present invention provides a monitor, especially a wake up monitor, for monitoring an integrated circuit, the monitor comprising a first monitoring unit configured to monitor at least one input of the integrated circuit, a second monitoring unit configured to monitor at least one output of the integrated circuit, a measurement unit configured to measure the time elapsed between an event on the at least one input and a reaction to the event on the at least one output and configured to output an alert signal if the elapsed time exceeds a predetermined first time limit. The present invention furthermore discloses an integrated circuit and a method for monitoring an integrated circuit.

Abstract: A processor system includes at least two processor cores and an interrupt controller including interrupt priority registers configured for registering interrupt priorities of the respective processor cores. The processor system further includes at least two task timers associated with respective processor cores. Each task timer includes a counter configured for producing a counter value, a timeout value register configured for storing a timeout value and a tidemark value register configured for storing a tidemark value smaller than the timeout value. Each task timer is configured for producing a timeout signal when the counter value equals the timeout value and for producing a tidemark signal when the counter value equals the tidemark value. The interrupt controller is configured for increasing the interrupt priority of a processor core in response to a tidemark signal and for decreasing the interrupt priority of a processor core in response to a timeout signal.

Abstract: High frequency detection of interrupts includes incrementing a count by a first number in response to at least one interrupt. The count is decremented by a second number in response to a clock if the count is greater than zero. An interrupt rate is determined from the count. A fault collection unit (FCU) is updated when the interrupt rate exceeds a threshold.

Abstract: In a system on chip SoC, a memory control unit connected between the memory unit and the processing unit controls access to the memory unit. An update request received or generated by the processing unit triggers an update operation which comprises appending an update enabling record to a sequence of update records in the log region, writing new program code to the memory unit, and appending an update completion record to a sequence of update records. Write access to the log region is disabled if a fault is detected in the SoC during the update operation.

Abstract: The present application provides a calibration device for calibrating a crank angle of a calibrateable combustion engine, the calibrateable combustion engine and a method for calibrating. The calibration device is provided to determine a trigger wheel angle offset from a combustionless driving of the combustion engine in that an in-cylinder pressure profile is recorded, on the basis of which a trigger wheel angle offset is determined and stored at an offset memory of the combustion engine. The combustion engine is configured to determine a crank angle on the basis of a measured trigger wheel angle and the stored trigger wheel angle offset.

Abstract: A method of detecting overcurrent events within at least one electronic device, and an overcurrent detection module therefor. The method comprises receiving at least one current requirement indication from at least one electronic device, determining at least one overcurrent value based at least partly on the received at least one current requirement indication, receiving at least one indication of at least one input current flow for the at least one electronic device, and determining that an overcurrent event is occurring if the indicated at least one input current flow for the at least one electronic device exceeds the determined at least one overcurrent value.

Abstract: A peripheral integrated circuit (IC) device for providing support to a data processing IC device. The peripheral IC device comprises a fault detection component arranged to detect an occurrence of fault conditions within the data processing IC device. The peripheral IC device further comprises a safe state control component. Upon detection of a fault condition occurring within the data processing IC device by the fault detection component, the safe state control component is arranged to cause at least one I/O cell of the data processing IC device to be configured into at least one scan-chain, and cause at least one predefined control signal to be scanned into the at least one scan-chain to configure the at least one I/O cell into a state corresponding to the predefined control signal.