Abstract: A low leakage CMOS analog switch circuit comprising conventional MOS switches having transistors of high threshold voltages coupled to an interface circuit comprising transistors of low threshold voltages is provided. The N-channel threshold voltage of transistors in the switches is adjusted upward and the P-channel threshold voltage of transistors in the interface circuit is adjusted downward through the use of a single mask in one process step.

Abstract: A complementary field effect transistor integrable voltage regulator suitable for use in CMOS integrated circuits includes first and second regulator sections coupled together. One regulator section includes a P channel MOSFET and an N channel MOSFET and a resistor, the P channel MOSFET and the resistor being coupled in series between an internal supply conductor and a reference conductor, the N channel MOSFET being connected in parallel therewith and having its gate electrode connected to the junction between the P channel MOSFET and the resistor. The gate electrode of the P channel MOSFET is connected to the output of another regulator, which includes a zener diode and a resistor coupled in series between the reference conductor and another voltage conductor.

Abstract: A CMOS logic circuit having a basic CMOS shift register useful as a shift register or in sequential logic circuits is provided. The circuit has two inverters plus an output inverter and two transistors which are enabled by a clock signal to couple the inverters together. The use of a single input clock signal along with the reduced number of transistors is achieved by proper selection of threshold voltages of the transistors.

Abstract: A CMOS regulated constant current circuit includes a first reference circuit producing a reference voltage applied to one input of an operational amplifier. The output of the operational amplifier is connected to the gate electrode of a reference field effect transistor having its source connected to ground and its drain connected to the other input of the operational amplifier and to one terminal of a control resistor, the other terminal of the reference field effect transistor being coupled to a plurality of CMOS transmission gates. Each of the CMOS transmission gates can controllably be switched on independently in order to apply the operational amplifier output voltage to a respective one of a plurality of output field effect transistors of the same conductivity type as the reference field effect transistor and each having its source connected to ground.

Abstract: A complementary field effect transistor integrated circuit includes an input buffer, internal high density logic circuitry having a collapsed guard ring structure associated therewith, an internal power source which provides operating voltage for the internal high density logic lower than the junction reverse breakdown voltage of the collapsed guard ring structure, and an output level shifter circuit. The output level shifter circuit and input buffer, and internal power source have a conventional non-collapsed guard ring structure associated therewith.