Patents by Inventor Allan C. Toriaga

Allan C. Toriaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8236612
    Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: August 7, 2012
    Assignee: Unisem (Mauritius) Holdings Limited
    Inventors: Romarico S. San Antonio, Michael H. McKerreghan, Anang Subagio, Allan C. Toriaga
  • Publication number: 20120126378
    Abstract: A package for a semiconductor device includes shielding from RF interference. The package has a lead frame with a lead and a connecting bar. The lead has an inner end for connecting to the device and an outer end having an exposed surface at the package side face. The connecting bar also has an end with an exposed surface at the package side face. A molding compound overlying the leadframe forms a portion of the side face. Electrically conductive shielding forms a top surface of the package, and extends downward therefrom to form an upper portion of the package side face. The exposed surface at the connecting bar end has an upper edge higher than the upper edge of the exposed surface of lead end. Accordingly, the shielding makes electrical contact with the connecting bar adjacent to its exposed surface, while being electrically isolated from the lead.
    Type: Application
    Filed: November 24, 2010
    Publication date: May 24, 2012
    Applicant: Unisem (Mauritius ) Holdings Limited
    Inventors: Romarico S. San Antonio, Michael H. McKerreghan, Anang Subagio, Allan C. Toriaga
  • Patent number: 8084300
    Abstract: A method for manufacturing a semiconductor device package to provide RF shielding. The device is mounted on a laminated substrate having conducting pads on its top surface. A molding compound covers the substrate top surface and encapsulates the devices. The substrate is disposed on a tape; the molding compound and the substrate are cut through, forming package units separated by the saw cut width and exposing a portion of a conducting pad. In an embodiment, the tape is stretched to widen the gap between package units. A conductive shield is applied to cover each package unit and to make electrical contact with the exposed conducting pad portion, thereby connecting to a ground trace beneath the device and providing RF shielding for the device. A single-unit molding process may be used, in which the conducting pad is exposed during and after molding.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: December 27, 2011
    Assignee: Unisem (Mauritius) Holdings Limited
    Inventors: Romarico S. San Antonio, Michael H. McKerreghan, Anang Subagio, Allan C. Toriaga, Lenny Christina Gultom
  • Publication number: 20110111562
    Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.
    Type: Application
    Filed: January 19, 2011
    Publication date: May 12, 2011
    Inventors: Romarico S. San Antonio, Michael H. McKerreghan, Anang Subagio, Allan C. Toriaga