Patents by Inventor ALLAN HE

ALLAN HE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10845979
    Abstract: A method for displaying digital content in an interactive navigation interface is provided. The method includes: displaying a plurality of top-level category groups on a display screen; receiving a user pointing operation selecting one of the top-level category groups from a remote controller; providing visual feedback for the selected top-level category group; and in response to a zoom-in operation on the selected top-level category group received from the remote controller, displaying a plurality of digital content objects within the selected top-level category group.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: November 24, 2020
    Assignee: TCL RESEARCH AMERICA, INC.
    Inventors: Di Meng, Haohong Wang, Allan He
  • Publication number: 20200225822
    Abstract: A method for displaying digital content in an interactive navigation interface is provided. The method includes: displaying a plurality of top-level category groups on a display screen; receiving a user pointing operation selecting one of the top-level category groups from a remote controller; providing visual feedback for the selected top-level category group; and in response to a zoom-in operation on the selected top-level category group received from the remote controller, displaying a plurality of digital content objects within the selected top-level category group.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 16, 2020
    Inventors: Di MENG, Haohong WANG, Allan HE
  • Patent number: 8884374
    Abstract: Various embodiments provide complementary metal-oxide-semiconductor (CMOS) devices and their fabrication methods. A semiconductor substrate is provided to include a first region to form a PMOS transistor and a second region to form an NMOS transistor. One of the first and second regions can include a metal gate structure having a metal top layer. The other of the first and second regions can include an interfacial oxide layer formed on a high-k dielectric layer. A surface of the metal top layer can be oxidized to form a metal oxide top layer covering the metal top layer. The metal oxide top layer and the interfacial oxide layer can be removed by wet etching. A metal gate can be formed on the high-k dielectric layer.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: November 11, 2014
    Assignee: Semiconductor Manufacturing International Corp.
    Inventors: Leo Liu, Allan He
  • Patent number: 8846475
    Abstract: A method for fabricating a semiconductor device comprises providing a substrate having a core oxide layer and an I/O oxide layer formed thereon. The I/O oxide layer has an I/O mask layer formed thereon. The method also includes forming an I/O dummy gate on the I/O mask layer and a core dummy gate on the core oxide layer, forming an etch barrier layer on the substrate covering the dummy gates, forming a dielectric layer on the etch barrier layer, and planarizing the etch barrier layer and the dielectric layer to expose the top surface of the dummy gates. The method further includes simultaneously removing the I/O and core dummy gates to form I/O and core gate grooves, removing the core oxide layer, removing the I/O mask layer, depositing a dielectric layer in the core gate groove, and forming a metal gate layer filling the I/O and core gate grooves.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Allan He
  • Publication number: 20140187006
    Abstract: A method for fabricating a semiconductor device comprises providing a substrate having a core oxide layer and an I/O oxide layer formed thereon. The I/O oxide layer has an I/O mask layer formed thereon. The method also includes forming an I/O dummy gate on the I/O mask layer and a core dummy gate on the core oxide layer, forming an etch barrier layer on the substrate covering the dummy gates, forming a dielectric layer on the etch barrier layer, and planarizing the etch barrier layer and the dielectric layer to expose the top surface of the dummy gates. The method further includes simultaneously removing the I/O and core dummy gates to form I/O and core gate grooves, removing the core oxide layer, removing the I/O mask layer, depositing a dielectric layer in the core gate groove, and forming a metal gate layer filling the I/O and core gate grooves.
    Type: Application
    Filed: July 31, 2013
    Publication date: July 3, 2014
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: ALLAN HE
  • Publication number: 20140015065
    Abstract: Various embodiments provide complementary metal-oxide-semiconductor (CMOS) devices and their fabrication methods. A semiconductor substrate is provided to include a first region to form a PMOS transistor and a second region to form an NMOS transistor. One of the first and second regions can include a metal gate structure having a metal top layer. The other of the first and second regions can include an interfacial oxide layer formed on a high-k dielectric layer. A surface of the metal top layer can be oxidized to form a metal oxide top layer covering the metal top layer. The metal oxide top layer and the interfacial oxide layer can be removed by wet etching. A metal gate can be formed on the high-k dielectric layer.
    Type: Application
    Filed: January 18, 2013
    Publication date: January 16, 2014
    Inventors: LEO LIU, ALLAN HE