Patents by Inventor Allan Ilagan

Allan Ilagan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RELIABLE SEMICONDUCTOR PACKAGES
    Publication number: 20210366963
    Abstract: A semiconductor package is disclosed. The package includes a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die region. A die having first and second major die surfaces is attached onto the die region. The second major die surface is attached to the die region. The first major die surface includes a sensor region and a cover adhesive region surrounding the sensor region. The package also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the sensor region. The protective cover includes a recessed structure on the second major cover surface.
    Type: Application
    Filed: August 4, 2021
    Publication date: November 25, 2021
    Inventors: Il Kwon SHIM, Jeffrey PUNZALAN, Emmanuel ESPIRITU, Allan ILAGAN, Teddy Joaquin CARREON
  • Integrated circuit package system with heatspreader
    Patent number: 8395254
    Abstract: An integrated circuit package system includes providing a substrate having an integrated circuit, attaching a heatspreader having a force control protrusion on the substrate, and forming an encapsulant over the heatspreader and the integrated circuit.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: March 12, 2013
    Assignee: STATS Chippac Ltd.
    Inventors: Emmanuel Espiritu, Dario S. Filoteo, Jr., Leo A. Merilo, Philip Lyndon Cablao, Rachel Layda Abinan, Allan Ilagan
  • Integrated circuit package system having interconnect stack and external interconnect
    Patent number: 8138080
    Abstract: An integrated circuit package system is provided forming an integrated circuit die having a first bond pad provided thereon, forming an interconnect stack on a first external interconnect, and connecting the interconnect stack to the first bond pad.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: March 20, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Dario S. Filoteo, Jr., Leo A. Merilo, Philip Lyndon Cablao, Emmanuel Espiritu, Rachel Layda Abinan, Allan Ilagan
  • Stacked integrated circuits package system with passive components
    Patent number: 8026129
    Abstract: A stacked integrated circuit package system is provided forming a first stack layer having a first integrated circuit die on a first substrate, forming a second stack layer having a second integrated circuit die on a second substrate, and mechanically and electrically connecting a spacer layer having a first passive component between the second stack layer and the first stack layer.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: September 27, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Philip Lyndon Cablao, Dario S. Filoteo, Jr., Leo A. Merilo, Emmanuel Espiritu, Rachel Layda Abinan, Allan Ilagan
  • INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEATSPREADER
    Publication number: 20070235859
    Abstract: An integrated circuit package system includes providing a substrate having an integrated circuit, attaching a heatspreader having a force control protrusion on the substrate, and forming an encapsulant over the heatspreader and the integrated circuit.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 11, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Emmanuel Espiritu, Dario Filoteo, Leo Merilo, Philip Cablao, Rachel Abinan, Allan Ilagan
  • STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM WITH PASSIVE COMPONENTS
    Publication number: 20070210432
    Abstract: A stacked integrated circuit package system is provided forming a first stack layer having a first integrated circuit die on a first substrate, forming a second stack layer having a second integrated circuit die on a second substrate, and mechanically and electrically connecting a spacer layer having a first passive component between the second stack layer and the first stack layer.
    Type: Application
    Filed: March 10, 2006
    Publication date: September 13, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Philip Cablao, Dario Filoteo, Leo Merilo, Emmanuel Espiritu, Rachel Abinan, Allan Ilagan
  • INTEGRATED CIRCUIT PACKAGE SYSTEM
    Publication number: 20070210436
    Abstract: An integrated circuit package system is provided forming an integrated circuit die having a first bond pad provided thereon, forming an interconnect stack on a first external interconnect, and connecting the interconnect stack to the first bond pad.
    Type: Application
    Filed: March 10, 2006
    Publication date: September 13, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Dario Filoteo, Leo Merilo, Philip Cablao, Emmanuel Espiritu, Rachel Abinan, Allan Ilagan