Abstract: A random access memory (RAM) complex that can concurrently read and write to different addresses. The memory complex includes two RAMs, each having an address selector, includes a data out multiplexer for selecting outputs from one of the RAM's. A tag array stores an array of tag, one for each address in the RAM's. The tag marks which one of the two RAM's has the valid data for the corresponding read address. During a concurrent read and write cycle, the tag selects the read address for one RAM, selects the write address for the other RAM and a staged copy of the tag controls the multiplexer to select data from the correct RAM for the data out.

Abstract: A timer unit that permits individual timer registers to be taken offline from the timer complex. A single register is taken offline instead of checkstopping the entire computer system due to a damaged timer, for example, thereby reducing system outages and thus providing increased availability of the system.

Abstract: A computer system having a number of circuits and error detection circuitry for detecting errors in the circuits and providing error signals. Error recovery is provided by detecting an error with checking logic, turning off system clocks and invoking error recovery software, executing recovery software to recover from the error and set an action latch, turning on system clocks, taking hardware recovery action in response to the action latch, resetting the action latch and continue processing. Action latches are used extensively throughout the computer system.

Abstract: In a data processing apparatus, having a user domain with domain storage space and an emulation domain with emulation storage space, emulates an instruction in the user domain by calling a program of instructions in the emulation domain. An instruction register connected to receive the sequence of instructions is partitioned into a plurality of fields. At least one field of the instruction register identifies a location for address information for an operand used in execution of the instruction. The instruction is decoded to generate a control code. The control code includes a branch signal to call the emulation program and a domain access control signal to indicate whether the emulation program requires access to the user domain storage base for execution. During execution of the emulation routine, domain access is implied by the location identified for the address information--a set of locations having been preselected as address registers for implied domain addressing.

Abstract: A central processor architecture implementating a deterministic, digit based, subterm computation and selective subterm combination early condition code analysis mechanism to provide for the early determination of the condition code that will be returned upon normal execution of a condition code setting instruction is described. The early condition code is returned sufficiently early to be combined with a branch mask to substantially reduce if not eliminate the need to interlock an immediately following conditional branch instruction. A wide variety of condition code setting instructions are handled by the deterministic condition code analysis mechanism of the present invention by implementing the mechanism to determine condition codes by the generation of digit subterms of the operand data accompanying condition code setting instruction and then combining the digit subterms in a predetermined manner selected based on the specific condition code setting instruction being executed.

Abstract: An apparatus and method for use in improving cache storage unit utilization during an interlock of an instruction pipeline generates a control signal during one cycle of the interlock if the interlocked instruction may require storage unit management work. In response to the control signal, selector control logic in the storage unit generates a priority signal indicating the interlocked instruction for selection by the storage unit for processing. In response to the control signal and the priority signal, the cache management logic is used during the interlock on the interlocked instruction to prepare for supplying needed data when the interlock is released.

Abstract: An interlock of an instruction processing pipeline in a data processing system responsive to the validity of the pipeline stages within the instruction unit pipeline under microprogram control, is provided. Thus, a microprogram can provide for the release of a particular pipeline stage based on a selected characteristic of the valid signals generated by other stages of the pipeline. An interlock control signal is generated by a decode of a field in a microinstruction stored in a control store RAM or through hardwired decoding.

Abstract: The present invention provides for use in a data processor a method for mapping a respective machine language instruction stored by cache storage unit to a respective microprogrammed algorithm stored in control storage unit means, wherein the respective machine language instruction includes an opcode field with a prescribed value and at least one nonopcode field with one of a plurality of values, the method, comprising the steps of in the course of one data processor clock cycle, providing the respective machine language instruction to a decoder for converting the prescribed opcode field and the at least one nonopcode field of the respective machine language instruction into a respective combination of decoded signals which corresponds to the prescribed opcode field value and that at least one nonopcode field value of the respective machine language instruction; and providing the respective combination of decoded signals to combinational logic for converting the respective combination of decode signals into a

Abstract: In a data processing apparatus, having a user domain with domain storage space and an emulation domain with emulation storage space, emulates an instruction in the user domain by calling a program of instructions in the emulation domain. An instruction register connected to receive the sequence of instructions is partitioned into a plurality of fields. At least one field of the instruction register identifies a location for address information for an operand used in execution of the instruction. The instruction is decoded to generate a control code. The control code includes a branch signal to call the emulation program and a domain access control signal to indicate whether the emulation program requires access to the user domain storage base for execution. During execution of the emulation routine, domain access is implied by the location identified for the address information--a set of locations having been preselected as address registers for implied domain addressing.