Abstract: A data processing apparatus 2 includes error detection and correction circuitry 8 with an associated hard-error memory buffer 10. When a correctable hard-error is detected associated with a memory access to a memory 6, if the hard-error memory buffer 10 is already full, then this correctable hard-error is escalated to be handled as an uncorrectable hard-error. The escalated uncorrectable hard-error is then handled by uncorrectable error handling circuitry 14 (fatal error circuitry) which may trigger an abort of corresponding processing operations by a processor core 4 and force the relinquishing of resources within other circuit elements such as a store buffer 16.

Abstract: A multithreading processor 4 interleaves program instructions from different program threads to perform fine grained multithreading. Thread performance monitoring circuitry 30 monitors performance parameters of individual program threads to generate performance values. Issue control circuitry 28 reads these performance values to determine which program thread is next selected to be active when a thread switch event occurs. The performance parameters measured may include the proportion of cycles in which a program thread is able to provide a program instruction for execution by the execution circuitry 12 within the processor 4.

Abstract: An integrated circuit 2 incorporates prefetch circuitry 12 for prefetching program instructions from a memory 6. The prefetch circuitry 12 includes a branch target address cache 28. The branch target address cache 28 stores data indicative of branch target addresses of previously encountered branch instructions fetched from the memory 6. For each previously encountered branch instructions, the branch target address cache stores a tag value indicative of a fetch address of that previously encountered branch instruction. The tag values stored are generated by tag value generating circuitry 32 which performs a hashing function upon a portion of the fetch address such that the tag value has a bit length less than the bit length of the portion of the fetch address concerned.

Abstract: A multithreading processor 4 interleaves program instructions from different program threads to perform fine grained multithreading. Thread performance monitoring circuitry 30 monitors performance parameters of individual program threads to generate performance values. Issue control circuitry 28 reads these performance values to determine which program thread is next selected to be active when a thread switch event occurs. The performance parameters measured may include the proportion of cycles in which a program thread is able to provide a program instruction for execution by the execution circuitry 12 within the processor 4.

Abstract: A data processing and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from a memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in the cache for access by the processing circuitry. If a pre-decoded instruction crosses a cache line boundary, then checking circuitry in respect of selected types of pre-decoded instruction checks for consistency between the first portion of the pre-decoded instruction stored within a first cache line and a contiguous second portion of the pre-decoded instruction stored within a second cache line. If this consistency check is passed such that the two portions are self-consistent, then the pre-decoded instruction can be further decoded and issued.

Abstract: A data processing and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from a memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in the cache for access by the processing circuitry. If a pre-decoded instruction crosses a cache line boundary, then checking circuitry in respect of selected types of pre-decoded instruction checks for consistency between the first portion of the pre-decoded instruction stored within a first cache line and a contiguous second portion of the pre-decoded instruction stored within a second cache line. If this consistency check is passed such that the two portions are self-consistent, then the pre-decoded instruction can be further decoded and issued.