Abstract: A phase detector in a phase locked loop decoder includes a reactive circuit adapted to vary a clock frequency responsive to a signal representing the phase error between a clocking signal and an incoming data signal, to maintain synchronization of the clocking and data signals. A fast synchronization circuit of the phase detector is adapted to generate a clock-frequency-altering signal whenever selected inputs derived from the data and clocking signals occur simultaneously, thereby rapidly forcing the clocking signal toward synchronization with the data signal.