Abstract: Embodiments disclosed herein include diagnostic substrates and methods of using the diagnostic substrates to extract plasma parameters. In an embodiment, a diagnostic substrate comprises a substrate and an array of resonators across the substrate. In an embodiment, the array of resonators comprises at least a first resonator with a first structure and a second resonator with a second structure. In an embodiment, the first structure is different than the second structure.

Abstract: A Class AB amplifier has a control stage and a push-pull stage. The control stage has a programmable resistor that allows a floating constant voltage to applied to the push-pull stage such that the quiescent current of the amplifier is relatively low. The configuration enables the amplifier to operate properly at relatively low power-supply voltage levels. The amplifier can be configured as the output driver for an operational amplifier (op-amp) with a Miller compensation configuration that replaces the conventional Miller compensation resistor with a transistor that is part of the op-amp.

Abstract: A Class AB amplifier has a control stage and a push-pull stage. The control stage has a programmable resistor that allows a floating constant voltage to applied to the push-pull stage such that the quiescent current of the amplifier is relatively low. The configuration enables the amplifier to operate properly at relatively low power-supply voltage levels. The amplifier can be configured as the output driver for an operational amplifier (op-amp) with a Miller compensation configuration that replaces the conventional Miller compensation resistor with a transistor that is part of the op-amp.

Abstract: In one embodiment, a hybrid output buffer having both an H-bridge mode and a CML mode of operation includes a plurality of transistor switches arranged between an upper rail and a bottom rail. A first pair of the transistor switches couples between the upper rail and respective output nodes. A pair of resistors couples between the output nodes and a central node. During H-bridge mode, the hybrid output buffer controls a potential of the upper rail responsive to a feedback signal proportional to a difference between a potential of the central node and a common-mode voltage.

Abstract: A large multi-touch electronic whiteboard comprises a switch for switching to an external system from the internal system in response to the needs.

Abstract: A large multi-touch electronic whiteboard comprises: a swivel holder and a gravity sensor to adjust the screen rendering in response to the rotation of the screen; and a virtual key displayed on the screen for transmitting a tile to a mobile device via the Bluetooth device when the virtual key is clicked.

Abstract: A method of operating presentation through a multi-touch panel, comprises steps of providing a presenting module having a format transformation module, user interface generator and presenting/reading mode switching module to a system; activating the presenting module and display interface generated by the user interface generator on a multiple-touch panel of the system, wherein the interface generated by the user interface generator includes a shrinkage image area to display the non-activated file, an operation area to display file which is activated and a buffer zoon to allow a user drag file in the shrinkage image area to the operation area, thereby activating the dragged file.

Abstract: A multi-user operating system through a multi-touch panel comprises a processor; a storage medium coupled to the processor; a multiple touch panel coupled to the processor to sense multi-touch event by at least one user, followed by displaying instruction result corresponding to the multi-touch event; a display dividing module coupled to the processor to divide the multiple touch panel into at least two sub-display areas; multiple user operation module being stored in the storage medium to instruct the display dividing module to execute a multiple user mode or a single user mode, thereby allowing the multiple user manipulate virtual objects on the at least two sub-display areas, simultaneously.

Abstract: A method for operating computer objects and the computer program product thereof are disclosed, and they are utilized to a computer. The computer includes an operating interface which comprises defining a work region, function instruction list and a plurality of computer objects, and parts of the computer objects are chosen. The steps of the method comprises: an input device which is connected to a processing device in the computer for defining the position information of the input device, and a computer object which is chosen on the work region of the operating interface is clicked for operating the computer object; wherein a function instruction, which comprises actions of rotation, zoom in/zoom out, movement, of the computer object, is clicked for users to operate the computer object.

Abstract: A heat spreader and package structure utilizing the same. The heat spreader is embedded in an encapsulant of a package and above a chip therein, wherein the package has a substrate, having a molding gate, and the chip has a center and a corner which is the farthest from the molding gate. The spreader includes a base with a hollow portion therethrough, a plurality of support leads, protruding from the base, on the inner edge, and a cap plate, having a hole at least directly above a region between the center and the corner of the chip, fixed by the support leads to be above the hollow portion, the cap plate.

Abstract: A heat spreader and package structure utilizing the same. The heat spreader is embedded in an encapsulant of a package and above a chip therein, wherein the package has a substrate, having a molding gate, and the chip has a center and a corner which is the farthest from the molding gate. The spreader includes a base with a hollow portion therethrough, a plurality of support leads, protruding from the base, on the inner edge, and a cap plate, having a hole at least directly above a region between the center and the corner of the chip, fixed by the support leads to be above the hollow portion, the cap plate.

Abstract: A heat spreader and package structure utilizing the same. The heat spreader is embedded in an encapsulant of a package and above a chip therein, wherein the package has a substrate, having a molding gate, and the chip has a center and a corner which is the farthest from the molding gate. The spreader includes a base with a hollow portion therethrough, a plurality of support leads, protruding from the base, on the inner edge, and a cap plate, having a hole at least directly above a region between the center and the corner of the chip, fixed by the support leads to be above the hollow portion, the cap plate.

Abstract: A heat spreader and package structure utilizing the same. The heat spreader is embedded in an encapsulant of a package and above a chip therein, wherein the package has a substrate, having a molding gate, and the chip has a center and a corner which is the farthest from the molding gate. The spreader includes a base with a hollow portion therethrough, a plurality of support leads, protruding from the base, on the inner edge, and a cap plate, having a hole at least directly above a region between the center and the corner of the chip, fixed by the support leads to be above the hollow portion, the cap plate.

Abstract: A 3D package has: a three-dimensional (3D) package substrate, a land grid array (LGA) or quad flat no-lead (QFN) package mounted on the 3D package substrate, the LGA or QFN package having an LGA or QFN die on a first side of an LGA or QFN package substrate, and a second die mounted directly on a second side of the LGA or QFN package substrate opposite the first side.

Abstract: A data source circuit and a complementary data recovery circuit which can transmit and receive data at a higher rate than a conventional data source circuit which uses similar fabrication technology. A data source circuit of the present invention has an input for receiving a periodic source clock signal having a period T; a synchronization signal generator for generating, based on said downstream-clock signal, a series of one or more periodic synchronization signals having periods substantially equal to T, each synchronization signal being delayed from a previous synchronization signal; and a transmitter for transmitting one or more sub-words of a multi-bit data word, each sub-word having one or more bits, separate ones of said one or more sub-words being transmitted responsive to separate progressively delayed combined pairs of said synchronization signals. In a preferred embodiment of the present invention particularly suited for use in a point to point (e.g.

Abstract: A circuit is for re-synchronizing an event indication signal received from a foreign domain to generate a result indication signal that is re-synchronized to a host clock signal. The event indication signal is received from the foreign domain at a first input terminal; and a host clock signal is received at a second input terminal. Edge-triggered flip flop circuitry of the circuit has a clock input, a data input, and a data output. The clock input is coupled to the second input terminal and the data input is coupled to receive a latch output signal. The edge-triggered flip flop circuitry clocks the latch output signal to the data output of the flip flop circuitry, to generate a result event indication signal, in response to a transition in the host clock signal. Delay circuitry is coupled to the first input terminal to receive the event indication signal. The delay circuitry provides a delayed event indication signal having a phase that is delayed from the event indication signal.

Abstract: A data source circuit and a complementary data acquisition circuit which can transmit and receive data at a higher rate than a conventional data source circuit which uses similar fabrication technology. A data source circuit of the present invention has an input for receiving a periodic source clock signal having a period T; a synchronization signal generator for generating, based on said downstream-clock signal, a series of one or more periodic synchronization signals having periods substantially equal to T, each synchronization signal being delayed from a previous synchronization signal; and a transmitter for transmitting one or more sub-words of a multi-bit data word, each sub-word having one or more bits, separate ones of said one or more sub-words being transmitted responsive to separate progressively delayed combined pairs of said synchronization signals. In a preferred embodiment of the present invention particularly suited for use in a point to point (e.g.