Patents by Inventor Allan Porterfield
Allan Porterfield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134541Abstract: Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or “tiles”) can be coupled to a controller (e.g., an “orchestration controller”) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.Type: ApplicationFiled: September 21, 2023Publication date: April 25, 2024Inventors: Richard C. Murphy, Glen E. Hush, Vijay S. Ramesh, Allan Porterfield, Anton Korzh
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Publication number: 20240118830Abstract: A computational storage system includes a computational storage subsystem having a controller and a storage. The controller is configured to receive a work chunk from a host. The work chunk includes identification of an executable object and identification of a data object. The controller is further configured to locate the data object in the storage via the identification of the data object, obtain a copy of the data object in a memory of the controller, execute functions in the executable object on the data object in the memory of the controller to generate a result object, and convey the result object to a destination of the computational storage system.Type: ApplicationFiled: October 10, 2022Publication date: April 11, 2024Inventors: Richard Murphy, Allan Porterfield
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Publication number: 20240105260Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.Type: ApplicationFiled: September 29, 2023Publication date: March 28, 2024Inventors: Vijay S. Ramesh, Allan Porterfield
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Patent number: 11810618Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.Type: GrantFiled: November 1, 2021Date of Patent: November 7, 2023Assignee: Micron Technology, Inc.Inventors: Vijay S. Ramesh, Allan Porterfield
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Patent number: 11789653Abstract: Memory access control, as described herein, can leverage persistent memory to store data that is generally stored in a non-persistent memory. An example method for memory access control can include receiving, by control circuitry resident on a memory device, a memory access request targeting an address of a volatile (e.g., non-persistent) memory component of the memory device and determining characteristics of data associated with the targeted address. The method can further include accessing data at the targeted address of the volatile memory component in response to determining that the characteristics of the data meet a first criterion and accessing data at another address of a non-volatile memory component in response to determining that the characteristics of the data meet a second criterion.Type: GrantFiled: August 20, 2021Date of Patent: October 17, 2023Assignee: Micron Technology, Inc.Inventors: Vijay S. Ramesh, Allan Porterfield
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Patent number: 11768614Abstract: Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or “tiles”) can be coupled to a controller (e.g., an “orchestration controller”) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.Type: GrantFiled: February 5, 2021Date of Patent: September 26, 2023Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Glen E. Hush, Vijay S. Ramesh, Allan Porterfield, Anton Korzh
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Patent number: 11650941Abstract: Systems, apparatuses, and methods related to a computing tile are described. The computing tile may perform operations on received data to extract some of the received data. The computing tile may perform operations without intervening commands. The computing tile may perform operations on data streamed through the computing tile to extract relevant data from data received by the computing tile. In an example, the computing tile is configured to receive a command to initiate an operation to reduce a size of a block of data from a first size to a second size. The computing tile can then receive a block of data from a memory device coupled to the apparatus. The computing tile can then perform an operation on the block of data to extract predetermined data from the block of data to reduce a size of the block of data from a first size to a second size.Type: GrantFiled: October 6, 2021Date of Patent: May 16, 2023Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Glen E. Hush, Vijay Ramesh, Allan Porterfield, Anton Korzh
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Patent number: 11625591Abstract: Systems, apparatuses, and methods related to an extended memory neuromorphic component for performing operations in memory are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit and a memory array. The example apparatus can further include a communication subsystem coupled to the at least one of the plurality of computing devices and to a neuromorphic component. At least one of the plurality of computing devices can receive a request from a host to perform an operation, receive an indication of data to be access in a memory device to perform the operation, and send an indication to the neuromorphic component to monitor the data to be accessed. The neuromorphic component can intercept data and determine that a portion of the data should be flagged.Type: GrantFiled: June 26, 2020Date of Patent: April 11, 2023Assignee: Micron Technology, Inc.Inventors: Vijay S. Ramesh, Allan Porterfield
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Publication number: 20230055349Abstract: Memory access control, as described herein, can leverage persistent memory to store data that is generally stored in a non-persistent memory. An example method for memory access control can include receiving, by control circuitry resident on a memory device, a memory access request targeting an address of a volatile (e.g., non-persistent) memory component of the memory device and determining characteristics of data associated with the targeted address. The method can further include accessing data at the targeted address of the volatile memory component in response to determining that the characteristics of the data meet a first criterion and accessing data at another address of a non-volatile memory component in response to determining that the characteristics of the data meet a second criterion.Type: ApplicationFiled: August 20, 2021Publication date: February 23, 2023Inventors: Vijay S. Ramesh, Allan Porterfield
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Patent number: 11586355Abstract: Systems, apparatuses, and methods related to a selectively operable memory device are described. An example method corresponding to a selectively operable memory device can include receiving, by a resistance variable memory device, a command to operate the resistance variable memory device in a first mode or a second mode and operating the resistance variable memory device in the first mode or the second mode based, at least in part, on the received command to perform, in the first mode, a read operation or a write operation, or both, or, in the second mode, a compute operation. The method can further include performing, using a processing unit resident on the resistance variable memory device, the compute operation, the testing operation, or both based, at least in part, on a determination that the resistance variable memory device is operating in the second mode.Type: GrantFiled: September 20, 2021Date of Patent: February 21, 2023Assignee: Micron Technology, Inc.Inventors: Vijay S. Ramesh, Allan Porterfield
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Patent number: 11579882Abstract: Systems, apparatuses, and methods related to extended memory operations are described. Extended memory operations can include operations specified by a single address and operand and may be performed by a computing device that includes a processing unit and a memory resource. The computing device can perform extended memory operations on data streamed through the computing tile without receipt of intervening commands. In an example, a computing device is configured to receive a command to perform an operation that comprises performing an operation on a data with the processing unit of the computing device and determine that an operand corresponding to the operation is stored in the memory resource. The computing device can further perform the operation using the operand stored in the memory resource.Type: GrantFiled: March 25, 2021Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Glen E. Hush, Vijay S. Ramesh, Allan Porterfield, Anton Korzh
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Publication number: 20230025291Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.Type: ApplicationFiled: October 5, 2022Publication date: January 26, 2023Inventors: Vijay S. Ramesh, Allan Porterfield, Richard D. Maes
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Patent number: 11481317Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.Type: GrantFiled: June 26, 2020Date of Patent: October 25, 2022Assignee: Micron Technology, Inc.Inventors: Vijay S. Ramesh, Allan Porterfield, Richard D. Maes
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Publication number: 20220059163Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.Type: ApplicationFiled: November 1, 2021Publication date: February 24, 2022Inventors: Vijay S. Ramesh, Allan Porterfield
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Publication number: 20220027297Abstract: Systems, apparatuses, and methods related to a computing tile are described. The computing tile may perform operations on received data to extract some of the received data. The computing tile may perform operations without intervening commands. The computing tile may perform operations on data streamed through the computing tile to extract relevant data from data received by the computing tile. In an example, the computing tile is configured to receive a command to initiate an operation to reduce a size of a block of data from a first size to a second size. The computing tile can then receive a block of data from a memory device coupled to the apparatus. The computing tile can then perform an operation on the block of data to extract predetermined data from the block of data to reduce a size of the block of data from a first size to a second size.Type: ApplicationFiled: October 6, 2021Publication date: January 27, 2022Inventors: Richard C. Murphy, Glen E. Hush, Vijay Ramesh, Allan Porterfield, Anton Korzh
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Publication number: 20220004319Abstract: Systems, apparatuses, and methods related to a selectively operable memory device are described. An example method corresponding to a selectively operable memory device can include receiving, by a resistance variable memory device, a command to operate the resistance variable memory device in a first mode or a second mode and operating the resistance variable memory device in the first mode or the second mode based, at least in part, on the received command to perform, in the first mode, a read operation or a write operation, or both, or, in the second mode, a compute operation. The method can further include performing, using a processing unit resident on the resistance variable memory device, the compute operation, the testing operation, or both based, at least in part, on a determination that the resistance variable memory device is operating in the second mode.Type: ApplicationFiled: September 20, 2021Publication date: January 6, 2022Inventors: Vijay S. Ramesh, Allan Porterfield
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Publication number: 20210406166Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Inventors: Vijay S. Ramesh, Allan Porterfield, Richard D. Maes
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Publication number: 20210406653Abstract: Systems, apparatuses, and methods related to an extended memory neuromorphic component for performing operations in memory are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit and a memory array. The example apparatus can further include a communication subsystem coupled to the at least one of the plurality of computing devices and to a neuromorphic component. At least one of the plurality of computing devices can receive a request from a host to perform an operation, receive an indication of data to be access in a memory device to perform the operation, and send an indication to the neuromorphic component to monitor the data to be accessed. The neuromorphic component can intercept data and determine that a portion of the data should be flagged.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Inventors: Vijay S. Ramesh, Allan Porterfield
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Patent number: 11176065Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices coupled to one another. Each of the plurality of computing devices can include a processing unit configured to perform an operation on a block of data in response to receipt of the block of data. Each of the plurality of computing devices can further include a memory array configured as a cache for the processing unit. The example apparatus can further include a first plurality of communication subsystems coupled to the plurality of computing devices and to a second plurality of communication subsystems. The first and second plurality of communication subsystems are configured to request and/or transfer the block of data.Type: GrantFiled: August 12, 2019Date of Patent: November 16, 2021Assignee: Micron Technology, Inc.Inventors: Vijay S. Ramesh, Allan Porterfield
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Patent number: 11164625Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.Type: GrantFiled: December 2, 2020Date of Patent: November 2, 2021Assignee: Micron Technology, Inc.Inventors: Vijay S. Ramesh, Allan Porterfield