Abstract: A differential phase shift keyed demodulator for demodulating a differential phase shift key modulated signal and synchronizing the clock thereof. To accomplish the demodulation, the differential phase shift keyed modulated signal is mixed with three reference signals offset by 120.degree.. This process creates three threshold boundaries in the XY vector phase plane and the three mixed signals are logically related to determine in which sector the instantaneous phase lies. The instantaneous phase at a first time is delayed for comparison with the instantaneous phase at a successive time. The result of this comparison process produces a signal representing the information. Synchronization of the data clock is accomplished by comparing the phase of the signal resulting from the demodulation at points midway between data decisions.

Abstract: SMSK data link degradation in future and immediate past bits produced by carrier phase error and small errors in the sampling instant are reduced by a recursive adaptive equalizer having a feedforward stage with adjustable weight for each future bit to be corrected and a feedback stage with adjustable weight for each immediate past bit to be corrected. The weights are controlled by a controller which samples the output and adjusts each weight until the output is correct.