Abstract: An integrated circuit is protected from reverse engineering by connecting doped circuit elements of like conductivity with a doped implant in the substrate, rather than with a metallized interconnect. The doped circuit elements and their corresponding implant interconnections can be formed in a common fabrication step with common implant masks, such that they have an integral structure with similar dopant concentrations. The metallization above the substrate surface can be designed to provide further masking of the interconnects, and microbridges can be added to span strips of transistor gate material in the interconnect path.

Abstract: An integrated circuit is protected from reverse engineering by connecting doped circuit elements of like conductivity with a doped implant in the substrate, rather than with a metallized interconnect. The doped circuit elements and their corresponding implant interconnections can be formed in a common fabrication step with common implant masks, such that they have an integral structure with similar dopant concentrations. The metallization above the substrate surface can be designed to provide further masking of the interconnects, and microbridges can be added to span strips of transistor gate material in the interconnect path.

Abstract: An integrated circuit is protected from reverse engineering by connecting doped circuit elements of like conductivity with a doped implant in the substrate, rather than with a metallized interconnect. The doped circuit elements and their corresponding implant interconnections can be formed in a common fabrication step with common implant masks, such that they have an integral structure with similar dopant concentrations. The metallization above the substrate surface can be designed to provide further masking of the interconnects, and microbridges can be added to span strips of transistor gate material in the interconnect path.

Abstract: Apparatus and method for detecting unauthorized disturbance of a protected surface, includes a substrate adapted to conformably encase and adhere to the surface that is to be protected. A plurality of layers, each comprising a plurality of frangible conduits is embedded in the substrate and randomly overlays a majority of the protected surface. Each of the conduits has its ends protruding from the substrate to permit a monitor to be coupled thereto for monitoring the integrity of the continuity of each conduits, and for switching from a first state to a second state whenever the continuity of any of the conduits is broken. A warning alarm is coupled to the monitor for displaying the state of the monitor.

Abstract: A set/scan test capability is provided for a circuit that includes sensitive subcircuits, but that can be latched out to prevent reverse engineering the sensitive elements. A mechanism to inhibit set/scan test access to at least some of the sensitive subcircuits is selectively actuated by a control circuit to override a normal set/scan test and inhibit set/scan access to the sensitive subcircuits. Various implementations are possible, such as fusible-link PROMs for irreversibly inhibiting set/scan access to the sensitive subcircuits after an initial non-inhibited test period, the use of encryption codes to enable repeated set/scan access to the sensitive subcircuits, and an erasable/reprogrammable mechanism for inhibiting set/scan access to programmed sets of subcircuits.