Abstract: A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory device. A selector, in line with a memory element, may be degraded with repeated temperature excursions as current passes through a stack during the read/write process. The selector changes from an amorphous state to become crystalline thus reducing the life of a memory device. The memory device includes a word line, a bit line disposed perpendicular to the word line, a stack—including a memory element, a selector, and a spacer—disposed between the word line and bit line, and one or more insulating layers surrounding an outer surface of the stack disposed between the word line and bit line. By surrounding the selector with a high thermal conductive heat-sink material, heat is directed away from the selector helping maintain the selector's amorphous state longer.

Abstract: Embodiments described herein generally relate to the use of three-dimensional solid state memory structures, both volatile and non-volatile, utilizing a Network-on-Chip routing protocol which provide for the access of memory storage via a router. As such, data may be sent to and/or from memory storage as data packets on the chip. The Network-on-Chip routing protocol may be utilized to interconnect unlimited numbers of three-dimensional memory cell matrices, spread on a die, or multiple dies, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits include a reduction in total density as compared to two-dimensional solid state memory structures utilizing a Network-on-Chip routing protocol, improved signal integrity, larger die areas, improved bandwidths and higher frequencies of operation.

Abstract: Embodiments of the present disclosure generally relate to non-volatile memory and, in particular, non-volatile memory with adjustable cell bit shapes. In one embodiment, an adjustable memory cell is provided. The memory cell generally includes a gate electrode, at least one recording layer and a channel layer. The channel layer generally is capable of supporting a depletion region and is disposed between the gate electrode and the at least one recording layer. In this embodiment, upon activating the gate, the channel layer may be depleted and current initially flowing through the channel may be steered through the at least one recording layer.

Abstract: A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory device. A selector, in line with a memory element, may be degraded with repeated temperature excursions as current passes through a stack during the read/write process. The selector changes from an amorphous state to become crystalline thus reducing the life of a memory device. The memory device includes a word line, a bit line disposed perpendicular to the word line, a stack—including a memory element, a selector, and a spacer—disposed between the word line and bit line, and one or more insulating layers surrounding an outer surface of the stack disposed between the word line and bit line. By surrounding the selector with a high thermal conductive heat-sink material, heat is directed away from the selector helping maintain the selector's amorphous state longer.

Abstract: The present disclosure generally relates to a nano-particle matrix in a 3D NVM RRAM device. The RRAM device utilizes a material that may be deposited into high aspect ratio channels, has good cycle ability, short erase and write times, and write/erase voltages that are compatible with CMOS. The RRAM material is disposed between two electrodes of the device and includes conductive nano-particles that are distributed within an insulating matrix. The particles are distributed below the percolation threshold.

Abstract: A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory device. A selector, in line with a memory element, may be degraded with repeated temperature excursions as current passes through a stack during the read/write process. The selector changes from an amorphous state to become crystalline thus reducing the life of a memory device. The memory device includes a word line, a bit line disposed perpendicular to the word line, a stack—including a memory element, a selector, and a spacer—disposed between the word line and bit line, and one or more insulating layers surrounding an outer surface of the stack disposed between the word line and bit line. By surrounding the selector with a high thermal conductive heat-sink material, heat is directed away from the selector helping maintain the selector's amorphous state longer.

Abstract: A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory device. A selector, in line with a memory element, may be degraded with repeated temperature excursions as current passes through a stack during the read/write process. The selector changes from an amorphous state to become crystalline thus reducing the life of a memory device. The memory device includes a word line, a bit line disposed perpendicular to the word line, a stack—including a memory element, a selector, and a spacer—disposed between the word line and bit line, and one or more insulating layers surrounding an outer surface of the stack disposed between the word line and bit line. By surrounding the selector with a high thermal conductive heat-sink material, heat is directed away from the selector helping maintain the selector's amorphous state longer.

Abstract: A method and apparatus for controlled switching of a magnetoresistive random access memory device is disclosed herein. The method includes delivering a current to a magnetoresistive random access memory device, wherein the MRAM device is in a first state, measuring a voltage drop across the magnetoresistive random access memory device in real-time with a resistance detector, wherein a voltage drop beyond a threshold voltage equates to switching from a first state to a second state, the first state different from the second state, determining whether the MRAM device has switched from the first state to the second state, and stopping the current delivered to the magnetoresistive random access memory device.

Abstract: A method and apparatus for controlled switching of a magnetoresistive random access memory device is disclosed herein. The method includes delivering a current to a magnetoresistive random access memory device, wherein the MRAM device is in a first state, measuring a voltage drop across the magnetoresistive random access memory device in real-time with a resistance detector, wherein a voltage drop beyond a threshold voltage equates to switching from a first state to a second state, the first state different from the second state, determining whether the MRAM device has switched from the first state to the second state, and stopping the current delivered to the magnetoresistive random access memory device.

Abstract: The present disclosure generally relates to a nano-particle matrix in a 3D NVM RRAM device. The RRAM device utilizes a material that may be deposited into high aspect ratio channels, has good cycle ability, short erase and write times, and write/erase voltages that are compatible with CMOS. The RRAM material is disposed between two electrodes of the device and includes conductive nano-particles that are distributed within an insulating matrix. The particles are distributed below the percolation threshold.

Abstract: Embodiments described herein generally relate to the use of three-dimensional solid state memory structures, both volatile and non-volatile, utilizing a Network-on-Chip routing protocol which provide for the access of memory storage via a router. As such, data may be sent to and/or from memory storage as data packets on the chip. The Network-on-Chip routing protocol may be utilized to interconnect unlimited numbers of three-dimensional memory cell matrices, spread on a die, or multiple dies, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits include a reduction in total density as compared to two-dimensional solid state memory structures utilizing a Network-on-Chip routing protocol, improved signal integrity, larger die areas, improved bandwidths and higher frequencies of operation.

Abstract: Embodiments of the present disclosure generally relate to memory devices having enhanced perpendicular magnetic anisotropy. The memory device includes a plurality of first leads, a plurality of second leads, and a plurality of memory cells having a plurality of magnetic layers and a tunneling barrier layer. An interfacial layer is incorporated in each memory cell between one of the magnetic layers and the tunneling barrier layer to enhance perpendicular magnetic anisotropy, while preserving high tunneling magnetoresistance.

Abstract: Embodiments of the present disclosure generally relate to non-volatile memory and, in particular, non-volatile memory with adjustable cell bit shapes. In one embodiment, an adjustable memory cell is provided. The memory cell generally includes a gate electrode, at least one recording layer and a channel layer. The channel layer generally is capable of supporting a depletion region and is disposed between the gate electrode and the at least one recording layer. In this embodiment, upon activating the gate, the channel layer may be depleted and current initially flowing through the channel may be steered through the at least one recording layer.

Abstract: Embodiments of the present disclosure generally relate to non-volatile memory and, in particular, non-volatile memory with adjustable cell bit shapes. In one embodiment, an adjustable memory cell is provided. The memory cell generally includes a gate electrode, at least one recording layer and a channel layer. The channel layer generally is capable of supporting a depletion region and is disposed between the gate electrode and the at least one recording layer. In this embodiment, upon activating the gate, the channel layer may be depleted and current initially flowing through the channel may be steered through the at least one recording layer.

Abstract: A magnetic recording disk drive determines the locations of defective bits in a failed data sector, and allows for the error correction code (ECC) to correctly decode the data from the sector. After a sector has failed decoding, the digitized waveform and the read channel state from the failed sector are stored in memory. A nondata pattern is written to the failed sector and read back to determine the locations of the defective data bits in the failed sector, which are then used to update the read channel state. The data pattern from the failed sector, with the identified bit error locations, is attempted to be decoded. If the decoding is successful then the sector is marked as bad and the correctly decoded data pattern is written to a different region of the disk, for example physical sectors specifically intended for use as spare sectors.

Abstract: A magnetic recording disk drive determines the locations of defective bits in a failed data sector, and allows for the error correction code (ECC) to correctly decode the data from the sector. After a sector has failed decoding, the digitized waveform and the read channel state from the failed sector are stored in memory. A nondata pattern is written to the failed sector and read back to determine the locations of the defective data bits in the failed sector, which are then used to update the read channel state. The data pattern from the failed sector, with the identified bit error locations, is attempted to be decoded. If the decoding is successful then the sector is marked as bad and the correctly decoded data pattern is written to a different region of the disk, for example physical sectors specifically intended for use as spare sectors.

Abstract: A magnetic recording disk has surface features of elevated lands and recessed grooves, and a planarized upper surface. A chemical-mechanical-polishing (CMP) stop layer is deposited over the lands and into the recesses. An adhesion film, like silicon, is deposited over the CMP stop layer, and fill material containing a silicon oxide (SiOx) is deposited over and in contact with the adhesion film. The adhesion film improves the adhesion of the SiOx fill material and prevents delamination during a subsequent two-step CMP planarizing process.

Abstract: A magnetic recording disk has surface features of elevated lands and recessed grooves, and a planarized upper surface. A chemical-mechanical-polishing (CMP) stop layer is deposited over the lands and into the recesses. An adhesion film, like silicon, is deposited over the CMP stop layer, and fill material containing a silicon oxide (SiOx) is deposited over and in contact with the adhesion film. The adhesion film improves the adhesion of the SiOx fill material and prevents delamination during a subsequent two-step CMP planarizing process.

Abstract: A magnetic recording disk with pre-patterned surface features of elevated lands and recessed grooves or trenches, like a discrete-track media (DTM) or bit-patterned media (BPM) disk, has a planarized surface. A multilayered disk overcoat is used to protect the recording layer, and at least one of the overcoat layers functions as a stop layer for terminating a chemical-mechanical polishing (CMP) process that substantially planarizes the disk. All of the layers of the multilayered overcoat are located above the lands, but none of the overcoat layers, or a number of layers less than the number of layers over the lands, is located above the recesses.