Patents by Inventor Allan Russell Martin
Allan Russell Martin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8387035Abstract: A scheduling algorithm is provided for selecting the placement of instructions with internal slack into a schedule of instructions within a loop. The algorithm achieves this by pinning nodes with internal slack to corresponding nodes on the critical path of the code that have similar properties in terms of the data dependency graph, such as earliest time and latest time. The effect is that nodes with internal slack are more often optimally placed in the schedule, reducing the need for rotating registers or register copy instructions. The benefit of the present invention can primarily be seen when performing instruction scheduling or software pipelining on loop code, but can also apply to other forms of instruction scheduling when greater control of placement of nodes with internal slack is desired.Type: GrantFiled: January 13, 2009Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventor: Allan Russell Martin
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Patent number: 8266610Abstract: A method, apparatus, and computer instructions for scheduling instructions for execution. Identify a series of instructions in a loop, wherein the series of instructions has a cyclic data dependency. Determine whether the series of instructions is a uniform series of instructions. Schedule execution of the uniform series of instructions within the loop to optimize execution of the loop in response to the identified series of instructions being the uniform series of instructions.Type: GrantFiled: September 19, 2008Date of Patent: September 11, 2012Assignee: International Business Machines CorporationInventor: Allan Russell Martin
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Patent number: 7962907Abstract: An improved scheduling technique for software pipelining is disclosed which is designed to find schedules requiring fewer processor clock cycles and reduce register pressure hot spots when scheduling multiple groups of instructions (e.g. as represented by multiple sub-graphs of a DDG) which are independent, and substantially identical. The improvement in instruction scheduling and reduction of hot spots is achieved by evenly distributing such groups of instructions around the schedule for a given loop.Type: GrantFiled: August 17, 2007Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Allan Russell Martin, James Lawrence McInnes
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Publication number: 20100095271Abstract: A mechanism for minimizing effective memory latency without unnecessary cost through fine-grained software-directed data prefetching using integrated high-level and low-level code analysis and optimizations is provided. The mechanism identifies and classifies streams, identifies data that is most likely to incur a cache miss, exploits effective hardware prefetching to determine the proper number of streams to be prefetched, exploits effective data prefetching on different types of streams in order to eliminate redundant prefetching and avoid cache pollution, and uses high-level transformations with integrated lower level cost analysis in the instruction scheduler to schedule prefetch instructions effectively.Type: ApplicationFiled: December 22, 2009Publication date: April 15, 2010Applicant: International Business Machines CorporationInventors: Roch Georges Archambault, Robert James Blainey, Yaoqing Gao, Allan Russell Martin, James Lawrence McInnes, Francis Patrick O'Connell
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Patent number: 7669194Abstract: A mechanism for minimizing effective memory latency without unnecessary cost through fine-grained software-directed data prefetching using integrated high-level and low-level code analysis and optimizations is provided. The mechanism identifies and classifies streams, identifies data that is most likely to incur a cache miss, exploits effective hardware prefetching to determine the proper number of streams to be prefetched, exploits effective data prefetching on different types of streams in order to eliminate redundant prefetching and avoid cache pollution, and uses high-level transformations with integrated lower level cost analysis in the instruction scheduler to schedule prefetch instructions effectively.Type: GrantFiled: August 26, 2004Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: Roch Georges Archambault, Robert James Blainey, Yaoqing Gao, Allan Russell Martin, James Lawrence McInnes, Francis Patrick O'Connell
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Patent number: 7546592Abstract: A method, computer program product, and a data processing system for scheduling instructions in a data processing system are provided. Dependencies among a plurality of nodes are analyzed to determine if any of the plurality of nodes uses a constrained resource. Each of the plurality of nodes represents an instruction in a set of instructions. A subset of the plurality of nodes is designated as resource-constrained nodes. An attempt is made to generate a schedule with the subset of the plurality of nodes scheduled with priority with respect to any of the plurality of nodes not included in the subset.Type: GrantFiled: July 21, 2005Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventor: Allan Russell Martin
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Publication number: 20090113184Abstract: A scheduling algorithm is provided for selecting the placement of instructions with internal slack into a schedule of instructions within a loop. The algorithm achieves this by pinning nodes with internal slack to corresponding nodes on the critical path of the code that have similar properties in terms of the data dependency graph, such as earliest time and latest time. The effect is that nodes with internal slack are more often optimally placed in the schedule, reducing the need for rotating registers or register copy instructions. The benefit of the present invention can primarily be seen when performing instruction scheduling or software pipelining on loop code, but can also apply to other forms of instruction scheduling when greater control of placement of nodes with internal slack is desired.Type: ApplicationFiled: January 13, 2009Publication date: April 30, 2009Applicant: International Business Machines CorporationInventor: Allan Russell Martin
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Patent number: 7506331Abstract: A method, apparatus, and computer instructions for processing instructions. A data dependency graph is built. The data dependency graph is analyzed for recurrences, and unpipelined instructions that lie outside of the recurrences are expanded.Type: GrantFiled: August 30, 2004Date of Patent: March 17, 2009Assignee: International Business Machines CorporationInventors: Roch Georges Archambault, Robert Frederick Enenkel, Robert William Hay, Allan Russell Martin, James Lawrence McInnes, Ronald Ian McIntosh, Mark Peter Mendell
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Patent number: 7493611Abstract: A scheduling algorithm is provided for selecting the placement of instructions with internal slack into a schedule of instructions within a loop. The algorithm achieves this by pinning nodes with internal slack to corresponding nodes on the critical path of the code that have similar properties in terms of the data dependency graph, such as earliest time and latest time. The effect is that nodes with internal slack are more often optimally placed in the schedule, reducing the need for rotating registers or register copy instructions. The benefit of the present invention can primarily be seen when performing instruction scheduling or software pipelining on loop code, but can also apply to other forms of instruction scheduling when greater control of placement of nodes with internal slack is desired.Type: GrantFiled: August 30, 2004Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventor: Allan Russell Martin
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Publication number: 20090013316Abstract: A method, apparatus, and computer instructions for scheduling instructions for execution. Identify a series of instructions in a loop, wherein the series of instructions has a cyclic data dependency. Determine whether the series of instructions is a uniform series of instructions. Schedule execution of the uniform series of instructions within the loop to optimize execution of the loop in response to the identified series of instructions being the uniform series of instructions.Type: ApplicationFiled: September 19, 2008Publication date: January 8, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Allan Russell Martin
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Patent number: 7444628Abstract: A method, apparatus, and computer instructions for scheduling instructions for execution. Identify a series of instructions in a loop, wherein the series of instructions has a cyclic data dependency. Determine whether the series of instructions is a uniform series of instructions. Schedule execution of the uniform series of instructions within the loop to optimize execution of the loop in response to the identified series of instructions being the uniform series of instructions.Type: GrantFiled: August 30, 2004Date of Patent: October 28, 2008Assignee: International Business Machines CorporationInventor: Allan Russell Martin
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Patent number: 7331045Abstract: An improved scheduling technique for software pipelining is disclosed which is designed to find schedules requiring fewer processor clock cycles and reduce register pressure hot spots when scheduling multiple groups of instructions (e.g. as represented by multiple sub-graphs of a DDG) which are independent, and substantially identical. The improvement in instruction scheduling and reduction of hot spots is achieved by evenly distributing such groups of instructions around the schedule for a given loop.Type: GrantFiled: April 29, 2004Date of Patent: February 12, 2008Assignee: International Business Machines CorporationInventors: Allan Russell Martin, James Lawrence McInnes
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Publication number: 20040268335Abstract: Instructions of a loop are related in instruction chains represented by a data dependency graph with multiple first nodes for the instruction chains (either in a backward or forward direction). These instructions are modulo scheduled for execution by a processor. Execution parameters for each instruction denote execution relationships with previous instructions including latencies from execution of previous instructions and processor resources used by the instruction for execution. The instructions are ordered for scheduling according to a priority value for each instruction, which may be determined in a number of ways. Ordering starts with all instructions that have the highest priority value. Ordering continues with instructions related to instructions that have already been ordered; those instructions that are related and have a given priority value for the unordered instructions. After all instructions have been ordered they are modulo scheduled.Type: ApplicationFiled: November 6, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATONInventors: Allan Russell Martin, James Lawrence Mcinnes