Patents by Inventor Allan Ward, III

Allan Ward, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120180844
    Abstract: Embodiments of a method and apparatus are described which provide a photovoltaic module in which light is diverted away from inactive areas of the photovoltaic module to active areas which generate electrical charges. A front support structure of a module is configured to redirect incident light to the active areas.
    Type: Application
    Filed: January 18, 2011
    Publication date: July 19, 2012
    Inventor: Allan Ward, III
  • Patent number: 7875545
    Abstract: A method of producing an ohmic contact and a resulting ohmic contact structure are disclosed. The method includes the steps of forming a deposited film of nickel and silicon on a silicon carbide surface at a temperature below which either element will react with silicon carbide and in respective proportions so that the atomic fraction of silicon in the deposited film is greater than the atomic fraction of nickel, and heating the deposited film of nickel and silicon to a temperature at which nickel-silicon compounds will form with an atomic fraction of silicon greater than the atomic fraction of nickel but below the temperature at which either element will react with silicon carbide. The method can further include the step of annealing the nickel-silicon compound to a temperature higher than the heating temperature for the deposited film, and within a region of the phase diagram at which free carbon does not exist.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: January 25, 2011
    Assignee: Cree, Inc.
    Inventors: Allan Ward, III, Jason Patrick Henning, Helmut Hagleitner, Keith Dennis Wieber
  • Patent number: 7858460
    Abstract: A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: December 28, 2010
    Assignee: Cree, Inc.
    Inventors: Zoltan Ring, Helmut Hagleitner, Jason Patrick Henning, Andrew Mackenzie, Scott Allen, Scott Thomas Sheppard, Richard Peter Smith, Saptharishi Sriram, Allan Ward, III
  • Patent number: 7696584
    Abstract: A semiconductor device is disclosed that includes a contact and an adjacent film on the surface of an underlying doped semiconductor material. The film has sufficient fixed charge to create an inversion layer adjacent the surface of the doped semiconductor material that under depletion conditions at least balances the number of surface states at the doping concentration of the underlying semiconductor material.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: April 13, 2010
    Assignee: Cree, Inc.
    Inventors: Jason P. Henning, Allan Ward, III
  • Patent number: 7598576
    Abstract: An improved termination structure for high field semiconductor devices in silicon carbide is disclosed. The termination structure includes a silicon carbide-based device for high-field operation, an active region in the device, an edge termination passivation for the active region, in which the edge termination passivation includes, an oxide layer on at least some of the silicon carbide portions of the device for satisfying surface states and lowering interface density, a non-stoichiometric layer of silicon nitride on the oxide layer for avoiding the incorporation of hydrogen and for reducing parasitic capacitance and minimizing trapping, and, a stoichiometric layer of silicon nitride on the nonstoichiometric layer for encapsulating the nonstoichiometric layer and the oxide layer.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: October 6, 2009
    Assignee: Cree, Inc.
    Inventors: Allan Ward, III, Jason Patrick Henning
  • Publication number: 20090215280
    Abstract: A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.
    Type: Application
    Filed: March 16, 2009
    Publication date: August 27, 2009
    Applicant: Cree, Inc.
    Inventors: Zoltan Ring, Helmut Hagleitner, Jason Patrick Henning, Andrew Mackenzie, Scott Allen, Scott Thomas Sheppard, Richard Peter Smith, Saptharishi Sriram, Allan Ward, III
  • Patent number: 7525122
    Abstract: A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: April 28, 2009
    Assignee: Cree, Inc.
    Inventors: Zoltan Ring, Helmut Hagleitner, Jason Patrick Henning, Andrew Mackenzie, Scott Allen, Scott Thomas Sheppard, Richard Peter Smith, Saptharishi Sriram, Allan Ward, III