Patents by Inventor Allegra R. Segura

Allegra R. Segura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8010838
    Abstract: Disclosed is a computer implemented method, data processing system, and apparatus to respond to detection of a hardware interface error on a system bus, for example, during a concurrent maintenance operation. The service processor may receive an error on the system bus. The error identifies at least one field replaceable unit and may inhibit the suppression of clock signal to the field replaceable unit. The service processor adds an identifier of the field replaceable unit to an eligible Field Replaceable Unit (FRU) list. The service processor recursively adds at least one field replaceable unit that the field replaceable unit depends upon. The service processor suppresses the clock signal to the field replaceable unit. The service processor inhibits tagging the field replaceable unit as unusable for next initial program load.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Sheldon Ray Bailey, Bradley W. Bishop, Alongkorn Kitamorn, Erlander Lo, Allegra R. Segura
  • Patent number: 7734902
    Abstract: According to a method of data processing in a data processing system, a hardware management component receives from a software component of the data processing system a request for management access to a hardware component of the data processing system. In response to receipt of the request for management access, the hardware management component determines whether or not the request contains a parameter indicative of the intended scope of hardware components to be accessed in response to the request. In response to the request, the hardware management component selects a scope in accordance with the determination and issues one or more hardware management commands to one or more target hardware components of the data processing system within the selected scope, such that an operating state of the one or more target hardware components is modified.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Daniel M. Crowell, Philip J. Sanders, Allegra R. Segura
  • Publication number: 20100125747
    Abstract: Disclosed is a computer implemented method, data processing system, and apparatus to respond to detection of a hardware interface error on a system bus, for example, during a concurrent maintenance operation. The service processor may receive an error on the system bus. The error identifies at least one field replaceable unit and may inhibit the suppression of clock signal to the field replaceable unit. The service processor adds an identifier of the field replaceable unit to an eligible Field Replaceable Unit (FRU) list. The service processor recursively adds at least one field replaceable unit that the field replaceable unit depends upon. The service processor suppresses the clock signal to the field replaceable unit. The service processor inhibits tagging the field replaceable unit as unusable for next initial program load.
    Type: Application
    Filed: November 20, 2008
    Publication date: May 20, 2010
    Applicant: International Business Machines Corporation
    Inventors: Sheldon Ray Bailey, Bradley W. Bishop, Alongkorn Kitamorn, Erlander Lo, Allegra R. Segura
  • Publication number: 20080141010
    Abstract: According to a method of data processing in a data processing system, a hardware management component receives from a software component of the data processing system a request for management access to a hardware component of the data processing system. In response to receipt of the request for management access, the hardware management component determines whether or not the request contains a parameter indicative of the intended scope of hardware components to be accessed in response to the request. In response to the request, the hardware management component selects a scope in accordance with the determination and issues one or more hardware management commands to one or more target hardware components of the data processing system within the selected scope, such that an operating state of the one or more target hardware components is modified.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 12, 2008
    Inventors: Daniel M. Crowell, Philip J. Sanders, Allegra R. Segura