Abstract: An instruction is presented to the cache; the instruction includes a cache control specifier which identifies a type of data being requested. Based on the cache control specifier, one of a plurality of replacement schemes is selected for swapping a data block out of the cache.

Abstract: A low overhead way for insuring that only routines of sufficient privilege can execute on a secured page of memory in an hierarchial computer system, and for raising the privilege level of a low privilege process in an orderly and secure way is presented. This is done through the execution of a single "gateway" branch instruction standing between a procedure call by a lower privileged routine, such as a user program, and an operating system itself.

Abstract: Memory integrity is maintained in a system with a hierarchical memory using a set of explicit cache control instructions. The caches in the system have two status flags, a valid bit and a dirty bit, with each block of information stored. The operating system executes selected cache control instructions to ensure memory integrity whenever there is a possibility that integrity could be compromised.

Abstract: A memory circuit for interconnection to a computer including several memory banks, each bank including memory for the storage of information for the total address space addressable by the data processor. The memory circuit further includes a bank selection circuit connected to the data processor for receiving data representing a selected one of the memory banks. The memory circuit further includes a memory access circuit that determines from the bank selection circuit which one of the memory banks has been selected and provides alternating access between the selected memory bank and a specific memory bank in accordance with a timing signal from the data processor. The specific data bank includes display information and is accessed by the data processor during each interval when information is being output to the display.