Abstract: A method is provided for forming a liquid phase epitaxial (LPE) germanium (Ge)-on-insulator (GOI) thin-film with a smooth surface. The method provides a silicon (Si) wafer, forms a silicon nitride insulator layer overlying the Si wafer, and selectively etches the silicon nitride insulator layer, forming a Si seed access region. Then, the method conformally deposits Ge overlying the silicon nitride insulator layer and Si seed access region, forming a Ge layer with a first surface roughness, and smoothes the Ge layer using a chemical-mechanical polish (CMP) process. Typically, the method encapsulates the Ge layer and anneals the Ge layer to form a LPE Ge layer. A Ge layer is formed with a second surface roughness, less than the first surface roughness. In some aspects, the method forms an active device in the LPE Ge layer.

Abstract: A planarized nanowire structure and a method for planarizing a nanowire structure are presented. The method provides nanowires with tips, formed overlying a substrate. A first insulator layer is deposited partially covering the nanowires. The first insulator layer is coated with a spin-on insulator layer, completely covering the nanowires. In some aspects of the method, the spin-on insulator layer is annealed. The spin-on insulator layer is then polished with a slurry and, in response to the polishing, a planarized insulator surface is formed with exposed nanowire tips.

Abstract: A method of fabricating a CMR layer in a CMOS device using CMP to pattern the CMR layer includes preparing a silicon substrate, including fabrication of a bottom electrode in the silicon substrate; depositing a layer of SiNx on the substrate; patterning and etching the SiNx layer to form a damascene trench over the bottom electrode; depositing a layer CMR material over the SiNx and in the damascene trench; removing the CMR material overlying the SiNx layer by CMP, leaving the CMR material in the damascene trench; and completing the CMOS structure.

Abstract: A method is provided for forming a liquid phase epitaxial (LPE) germanium (Ge)-on-insulator (GOI) thin-film with a smooth surface. The method provides a silicon (Si) wafer, forms a silicon nitride insulator layer overlying the Si wafer, and selectively etches the silicon nitride insulator layer, forming a Si seed access region. Then, the method conformally deposits Ge overlying the silicon nitride insulator layer and Si seed access region, forming a Ge layer with a first surface roughness, and smoothes the Ge layer using a chemical-mechanical polish (CMP) process. Typically, the method encapsulates the Ge layer and anneals the Ge layer to form a LPE Ge layer. A Ge layer is formed with a second surface roughness, less than the first surface roughness. In some aspects, the method forms an active device in the LPE Ge layer.

Abstract: A method of fabricating a CMR layer in a CMOS device using CMP to pattern the CMR layer includes preparing a silicon substrate, including fabrication of a bottom electrode in the silicon substrate; depositing a layer of SiNx on the substrate; patterning and etching the SiNx layer to form a damascene trench over the bottom electrode; depositing a layer CMR material over the SiNx and in the damascene trench; removing the CMR material overlying the SiNx layer by CMP, leaving the CMR material in the damascene trench; and completing the CMOS structure.

Abstract: Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses SSOI substrate fabrication processes comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is a two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

Abstract: Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses a SSOI substrate fabrication process comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is the two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.